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Webinar: SOI Gives More Performance Per Watt, And There's An Easy Path

Comments(0)Filed under: Digital Implementation, Low-Power , Power-Efficient Design, power analysis, low power, mixed signal, webinars, power, SOI, Silicon on Insulator

If you've seen any of the recent buzz lately around Silicon-On-Insulator (SOI), you'd know that it's an excellent option that can enable you to meet lower power consumption and die area targets without sacrificing performance or functionality. This is why Cadence, ARM and IBM have partnered to provide you an easy path to silicon with the SOI process for your digital design, including production proven software, design kits and IP.  

If you're a design manager or engineer, and you'd like to learn more about designing with SOI, please join Cadence and ARM on Wednesday August 25th for the "Ready for SOI" webinar. Here's more info:


August 25, 2010 @ 10:00 am pacific time

What & Where:

Attend this webinar to find out what SOI technology can do for you and how you can maximize its benefits. You'll learn how to implement and verify your digital and mixed signal SOI IP and SoCs, and you'll hear about how Cadence and its ecosystem partners are collaborating to offer an end-to-end SOI solution and methodology.

Register: http://www.secure-register.net/flyer.php?id=1160

This webinar is part of a Digital Implementation and Signoff series of webinars that begins August 24.

Michael Jacobs


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