Recently, there has been a lot of buzz about addressing DFM issues during routing. This is not a surprise as the economics of increased development cost of advanced process nodes and manufacturing has influenced dramatic changes to business models of several semiconductor companies. Due to the increasing design cost and time-to-market pressure, a re-design or few weeks delay, because of poor yield for example, may mean the financial death of a project and the subsequent loss of market window opportunity.At 45/40nm and advanced nodes, systematic variations are the greatest cause of catastrophic chip failures, and electrical issues related to timing, signal integrity and leakage power. Ideal-GDSII shapes (squares or rectangles) get converted into contours on silicon, irrespective of any post-tapeout manipulation of GDSII data. This is a leading cause of variability, leading to catastrophic and parametric failures. Signoff DFM has been available since the 65nm node and several EDA vendors have litho hotspot analysis tools. At 40nm, signoff DFM has been made a mandatory part of the tapeout flow by several leading foundries. In this area, Cadence’s Litho Physical Analyzer (LPA) has been the first to qualify at the leading foundries and is the industry’s fastest lithography hotspot detection solution. By leveraging proprietary algorithms, and distributed processing, LPA has proven to deliver near-linear scalability with each additional CPU.Model based litho hotspot detection is compute-intensive and depending on the type and complexity of the design the turnaround time can vary from few minutes to several hours. At Cadence, we integrated LPA with our flagship digital implementation solution – Encounter Digital Implementation System, at the 65nm node. While this was good, that is, signoff litho integration with implementation and leveraging a common database, the core problem remained – increased total design cycle time via iterative feedback loops from signoff to implementation.
How could we improve designers’ productivity and bring litho hotspot predictability in an incremental and convergent manner. Extreme care had to be taken such that by adding an additional DFM step during routing did not cause a big increase in turnaround time and thereby increase in design cycle time.
At the advent of the 65nm node, we launched in Encounter Digital Implementation System the industry’s first built-in litho prevention. In other words “in-route prevention” built in to Nanoroute has been successfully used in numerous 65 - 40nm production tapeouts and helped reduce the number of potential litho hotpots during routing. The whole flow is invisible to users and the technology and intelligence was built into the router. Customers simply enabled litho prevention, followed by a signoff run for complete litho hotspot identification and fixing.While “in-route” or “litho prevention” worked well for 65nm, and may be sufficient for some 40nm designs in eliminating a good chuck of the potential litho hotspots in a layout, the widening lithography manufacturing gap at 32/28nm leads to a dramatic increase in complexity. We have come to another point where existing technology (litho prevention or in-route DFM) is okay but not sufficient to enable designers with the best productivity ad predictability for their design flows.
At Cadence we have studied the growing lithography complexity problem and impact on design turnaround time and implemented yet another innovation in Encounter Digital Implementation System to help designers meet their design productivity and predictability goals. The goal is to help eliminate all potential litho hotspots during implementation and truly use signoff as a final verification step. I will explain the innovation in the Cadence approach in the coming weeks.
How are you managing DFM routing today? Let me know.