EDP Symposium Uncovers an Inconvenient Truth with a Shot of 3D

The nice thing about the EDP symposium (often referred to as the "secret DAC") is that it favors open discussions around presented papers. It is a sound mix of academic and industrial research and experiences and the goal is to foresee what the coming design problems might be and propose either solutions or alternatives. This year, the programme included a number of interesting topics including parallelism/cloud-computing for EDA, high level design/ESL, and 3D ICs.

I had the privilege to present on 3D IC design - particularly the latest work/trends around Through-Silicon Vias (TSV). For those of you that are new to this area, here's an interesting article that helps understand the foundational elements: http://www.cadence.com/Community/blogs/di/archive/2010/03/29/My-DATE-With-3DIC-Technology.aspx. The beauty and promise of this new technology is that it can inject a fresh breath of air into the semiconductor industry and give life to a whole new world of consumer end-applications. It can provide a huge paradigm shift to what can be achieved in design performance, power, and form factor.

The inconvenient truth is that the semiconductor industry is at crossroads. The cost of doing design in the traditional 2D methodology is getting exhorbitant. For instance, designing at 32/28nm incurs 3-4X the cost of design at 45nm (spanning fabrication costs, design costs, process and mask costs). Additional manufacturing effects like lithography, chemical-mechanical polishing, stress, and double-patterning are rendering the move to advanced process nodes exceedingly difficult. To make matters worse, we get hit with a double-whammy since the time-to-production on advanced process nodes has increased significantly, and that takes its toll on the profit margins for the industry.

And, this is where the new 3D/TSV solution shows promise to be the panacea to the industry's ailments. The biggest benefit it offers is the flexibility of heterogeneous integration. Designers no longer need to move the entire System-on-Chip (SoC) to the latest process node, thus eliminating a lot of the risks, costs and time-to-market delays. Design companies can choose to keep their analog, full-custom and memory IP at the older, safer process nodes while they move the aggressive CPU/GPU/digital logic to advanced process nodes. Essentially, designers now get the best-of-both-worlds by mitigating the cost, complexity, risk, and development time. And the end-result is smaller and faster and lower-power.

Thomas Williams from Future Tech and Sungkyu Lim from Georgia Tech also talked about 3D/TSV in their presentations. An interesting way of looking at the cost savings from 3D/TSV is the following: Let's take a traditional methodology for an SOC chip on a signle die with dimensions (L x L). The footprint/area of this device would be L² and the corner-to-corner distance would be 2L. Now consider this chip to be implemented in 3D as a stack of 4 dies with each die dimensions of (L/4 x L/4). The footprint/area of this device would be L²/4 (one fourth of the original). The corner-to-corner distance would be much smaller to the original as well (L + h, where h is the height of the stack).  And this reduced area and corner-to-corner wire-length is what effectively translates to significant benefits in performance and power for the 3D/TSV methodology.

In the real world, I see several semiconductor companies are now taping out real production chips. Some of them are also using "Silicon Interposers" which are silicon platforms with TSVs and enable different dies to be connected. It looks like the light at the end of the tunnel is real, and not just a false hope. While this technology and approach might not be for everybody (as was righly debated at the EDP symposium), it is certainly is a differentiating strategy for the select few semiconductor vendors who have embarked on this 3D/TSV path.

Have you looked at this 3D/TSV technology? What's your take on it?

-Rahul Deokar