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My DATE With 3DIC Technology

Comments(0)Filed under: Digital Implementation, CSV, 3DIC, DATE, TSV, PoP, flip chip, stacked die, wirebondThis year DATE (Design, Automation and Test in Europe) was in snowy cold Dresden, Germany, March 8th-March 12th and offered several 3DIC topics during the conference. I heard someone say "How did 3D with TSVs become hot from cold just so quickly?" In fact it did. Last year when I was following this technology I had found the design community to be hesitant in the feasibility of this technology in the beginning with lots of secretive projects in the pipeline. Suddenly by the end of last year, several IDMs, foundries, Cadence, and other EDA vendors were sharing methodologies and flows around 3D. There is now at least one discussion on this topic, at every industry conference, in various forms - panel, paper, etc.

For some of you who might be wondering what am I talking about let me share some background information: 3D is the stacking mechanism engineers have been using for several years to squeeze-in smaller package size to accommodate for smaller, denser electronic devices that consumers need and demand  (think cell phone, heart pace makers..tiny gadgets !!)


Added to that need of miniaturization is performance and density and that starts a trend called 3D TSV : It is a technology to stack chips on top of each other with a silicon layer in the middle with TSVs (Like Vias just too large) going between them. This helps performance, miniaturization and enables flexibility of combining Analog, RF, and Digital all on one package eliminating the need of wire bonding them down. Obviously as you may imagine this adds the complexity for the EDA tools to move from one dimension analysis to 3D knowledge.

Coming back to a more interesting topic - DATE in snowy Dresden, Germany.  DATE had 3 big 3D IC centric events - 3D tutorial session, 3D dinner event, and 3D Workshop.  I was able to attend the first and the last. I was pleasantly surprised to see two things: People's interest on this topic and actually given the newness of 3D with TSV technology, its increasing adoption by customers. I have to say "It is here today and it is taking off sooner than expected".

Both DATE 3D tutorial and Workshop had some good papers/presentations from EDA vendors and customers who have dared to be first in adopting 3D.  I noticed more sharing and more EDA players than last RTI conference I was in. From all the papers, talks, panels, keynotes one thing was clear that community is expecting EDA vendors to accelerate the tool development to support the growing 3D with TSV trend.  Apart from EDA vendors telling which part of the 3D flow they are enabling and helping out with, what also caught my attention are the questions that lingers around 3D :

  • Ecosystem readiness :
    • Are Foundries ready?
    • What will the business model look like between OSAT and Foundry?
  • Standards
    • Too many approaches (Via first, Via Last, Via Middle) today
    • How to do 3D test to answer questions on reliability and yield? (2 redundancy/4 redundancy approach, iJTAGs, KGD, TSV and Micro bump Fault modeling)
  • Cost of 3DICs with TSV vis-à-vis moving to the next smaller geometry

I think until and unless we find out the answers to the above, there will still be hesitation in the 3D wider adoption. In order for 3D TSV to really take off and become mainstream, I expect to see more close knit, open discussions and convergence on the above questions else it will remain just a niche technology !!

Samta  Bansal


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