Co-Design … some are trying to do it with spreadsheets … everyone is talking about it. But talk is cheap. Can you really optimize a package footprint and a chip I/O padring such that that package and PCB costs can be minimized?
What if using a straight forward flow you could take the devices to which your chip needs to interface and place them on a canvass with your chip and package. And then what if you could then see the maze of interconnect lines that crisscross in every imaginable direction giving you the daunting task of trying to figure out how to unravel that mess? But then, what if, with a few simple clicks of a mouse, you could turn …
Wouldn’t that make the routing your board and package easier? Wouldn’t that help keep costs down on your final product?
Yes, as a chip designer, you can look out into the package and board and optimize the full system. If you want to learn how Cadence SiP Digital Architect empowers chip designers to do just that, come see John Park’s webinar on August 26. You can register for the “SoC I/O Padring Optimization Using Cadence SiP Co-Design Technology” webinar by clicking here.
Please let us know what you think of the webinar.