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Noise Induced Double Clocking Explained

Comments(0)Filed under: Digital Implementation, encounter, double clocking, CadMOS, Enouter Timing System, CeltIC

In my previous blog on noise analysis accuracy, I mentioned something called “double-clocking” and a few of you since then have asked for more information on what it is... So as a follow-up to that bog, I’ve invited our resident noise analysis expert Trisha Kristof, who’s been working on our SI analysis since the CadMOS CeltIC days, to guest blog on this topic.

A note from Trisha Kristof on “Double Clocking”:

Double clocking happens when signals adjacent to the clock net switch in the opposite direction as the clock’s transition. If this causes a bump during the clocks transition, then double clocking can occur. Encounter Timing System actually looks at the worst opposite slope on clock nets when checking for double clocking. If this causes a clocking event on the receiving flop, we flag this as a double-clocking violation.




This is something we implemented back in in 2002 a customer who came to us to see if we could detect this situation which we subsequently implemented for them. Since creating this double clocking check, several customers using other solutions have come to us with silicon failures that were not detected. Running Encounter Timing System, they were able to find the failure right away.

Double clocking is just one of the advanced techniques we have evolved over the years since CeltIC was first announced in 2000 to ensure that your designs will not fail in silicon due to noise problems. We also employ advanced pessimism reduction algorithms to make sure that you don’t get overwhelmed with false noise violations during signoff.


Trisha Kristof
Staff Product Engineer
Cadence Design Systems


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