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Constraint Construction: What's Its Function? Part 4 of 4

Comments(4)Filed under: Digital Implementation, encounter, rtl compiler, design rules, modes of operation

This is the last in the series of Constraint Construction blogs! Today we're going to go over DESIGN RULES and MODES OF OPERATION.

DESIGN RULES: Follow them, or else...

Often times, these rules are indeed set in the timing library. But perhaps you want sharper transitions in your design to reduce noise issues. Or maybe you want to give yourself some margin of safety with minimum capacitance. Let's go over the main design rules to live by.

  • Max Fanout
    • How many cells should each instance drive?
    • Does the timing library set this at all or is it necessary for any specific library cells or instances in the design?
  • Min/Max Transition
    • What is the maximum slew that each pin in the system should have? Should you have max transitions on any input or output ports?
"So I cranked the max transition down to 100ps, and all my noise problems went away. Of course the design doesn't meet timing and is packed with buffers. But focusing on the good,... I got rid of the noise!"
  • Min/Max Capacitance
    • Should there be a limit to the load on each driving pin?
    • Perhaps even on an input port or internal net?
  • Design Environment
    • What timing library should we use?
    • Which timing corners (PVT)?
    • Will you be setting the operating conditions in the constraints?
"So you're saying there is a Best Case environment? Why would I care about that if it's so good?"

MODES OF OPERATION: There's more than one way to peel an apple.

Functional Mode(s)

  • Is there more than one functional mode?
    • Will one set of constraints handle all the modes?
    • If multiple modes will be used, are all the files correctly defining each mode correctly with the use of constants?
  • Test Mode(s)
    • Are there test modes that differ significantly from the functional operation (JTAG Boundary Scan, BIST/MBIST, Shift, and Capture)?
    • Have these been defined correctly as well?

Well, I hope this has been informative for everyone! The goal here is, whenever you get some constraints from someone, and you are not sure how well they are 'constructed', reference back to this and ask these simple questions and you just might catch problems early enough!

To read up some more on this topic, check out this section in the Encounter docs (please note, to access the doc requires and account and password): Setting Constraints and Performing Timing Analysis in Encounter RTL Compiler


Thomas Moore

Comments(4)

By Divya on July 14, 2009
I often wonder why there are 2 attributes: max_fanout and max_capacitance, in the library files. Aren't they both doing the same thing? What is the difference in the way these two values are determined for entry in the library?

By Thom Moore on July 15, 2009
Hi Divya,
My opinion is to ignore max_fanout and what REALLY matters is fixing that max_capacitance value.  In a way, they are doing the same thing, but the set_max_fanout has no idea the distances away any instances the driving pin are.  You could meet max_fanout but break max_cap because of a large net capacitance.
I don't often see max_fanout actually in libraries and only see the max_cap.  Within a liberty model (.lib), there are lookup tables which reference input slew and output capacitance.  The max_capacitance is simply the maximum that table goes.  It's basically saying beyond that cap value, we have no idea what the delay will be!   For max_fanout, usually they'll determine some input capacitance for a certain fanout that try to match that value up with max_cap.
Hope that helps explain it!
Thanks,
-Thom

By Aditya A. Patil on January 18, 2014
would like to know how to define constraints if i am writting code for a ripple carry adder where o/p of a FF is i/p clk to other???

By Kari on January 21, 2014
Hi Aditya, the author of this blog is no longer with Cadence. You can try posting your question to the forums. Thanks!

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