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'Back to School' in April? Are you Kidding?

Comments(0)Filed under: Digital Implementation, Manufacturability Sign-off, Low-Power , encounter, "SoC-Encounter", digital Implementationg, 8.1, low power, Encounter Digital Implementation System 8.1, encounter 8.1

No, I am not kidding. in fact, we have planned several 'back to school' seminars throughout the nation to tell you all about the latest technology in digital implementation. If you are a current customer using SoC Encounter, then you would want to check this out. If you recently adopted the new Encounter Digital Implementation System, then you also would want to attend.

Here is a short preview of what you can expect to hear at this event. If you find it interesting and would like to know more, then go to the registration site and read more about the event. 

Let me give you some additional information about Encounter Digital Implementation System. It was launched on December 3, 2008 as an ultra flexible, scalable, high-performance, high-capacity, RTL-GDSII design closure solution with extensibility to address low power, mixed signal, advanced node and signoff with a native multi-CPU enabled environment for today’s large, high performance, complex chips. 

Find out for yourself. Talk to Cadence R&D and network with the experts. This is an opportunity to sit shoulder-to-shoulder with individuals that are developing products such as this one and individuals that might be adopting and using Encounter Digital Implementation System. You can give feedback, receive feedback, and talk technical with the attendees and presenters. Don't take my word for it, register, attend, and see for yourself.

Here is a quick look at the agenda, dates and locations

9:00am Welcome & Introduction 
9:15am What's New in the Latest Version of the Encounter Digital IC Design Platform
9:30 am Design Closure - End-to-End, Multi-Core Flat & Hierarchical
11:00 am Break
11:15 am Mixed Signal - Integrated, Concurrent Analog and Digital
12:15 pm Lunch
1:00 pm Low Power - Advanced, Integrated Low-Power Implementation
2:00 pm Advanced Node - Comprehensive Manufacturing & Variation-Aware
2:45 pm Break
3:00 pm Analysis & Signoff - Integrated Timing, Power, Signal Integrity
4:00 pm Summary/Q&A

April 7, 2009 - San Jose, CA
April 9, 2009 - Austin, TX
April 21, 2009 - Tempe, AZ
April 29, 2009 - Chelmsford, MA

Click here for more information on the Back to School Seminars


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