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Demo: Partitioning a Design in SoC-Encounter

Comments(20)Filed under: Digital Implementation, screencast, SoC-Encounter, hierarchical design, partitioning

One of the longest standing capabilities in SoC-Encounter is its ability to partition a design- the process by which a design is broken up for hierarchical implementation.  I remember seeing "Big Chip? Go Hierarchical!" in marketing material for Silicon Perspective Corporation before I joined the company back in 2001 (Cadence acquired Silicon Perspective later that year), but it wasn't immediately obvious to me how the tool went about enabling hierarchical design.  I hope this quick demo gives you a feel for how partitioning occurs in SoC-Encounter:

If the video doesn’t automatically embed, please click here.

TCL commands used in this video:

  • specifyPartition
  • placeDesign
  • trialRoute
  • assignPtnPin
  • deriveTimingBudget
  • savePartition

Question of the Day: Have you used SoC-Encounter's partitioning capabilities?  If so, I'd like to hear about the scenarios where you've found it useful.  If not, I'd also be interested in hearing about any issues blocking you from using partitioning on your designs.



By Scrivner on November 7, 2008
I've tried using the partitioning flow but ran into problems with timing. It seemed that the timing budgeting was creating a constraints file with timing constraints that were impossible to meet. I submitted an SR on this months ago and haven't gotten an explanation or solution yet. It would be very useful to me if I could get the flow to work.

By BobD on November 7, 2008
Thanks for your comment!  I really appreciate your raising this issue.  Debugging timing budgeting failures is non-trivial (as I'm sure you've experienced).  When you say "timing constraints that were impossible to meet" it makes me think of scenarios where the external delay calculated by the tool exceeds available period come to mind.  Was that the case?  Or was it something different altogether?  In general, if it technically possible to meet timing when the design is timed flat at the top level (with virtual optimization enabled, which it is by default) then the timing constraints generated should be achievable.  However, if timing isn't achievable flat at the top level I think the correct thing for the tool to do is generate unachievable budgets (otherwise upon reassembly timing wouldn't be met and we'd complain about different problems as users).  I doubt that's the case in your service request, but without knowing more about the scenario it's hard to say.  I'll follow-up with a private message to see if I can help push your issue along internally.  Thanks for giving us the opportunity to address your issue and improve our software in the process.

By Scrivner on November 12, 2008
Thanks for comments Bob. I timed the design flat and timing was met with no problem. After partitioning, the constraints for the partitions had delays that exceeded the total clock period as you guessed. I'm new to the hierarchical flow so I don't have enough experience to understand whether the problem is something I'm doing wrong or if it's a tool bug which is why I submitted it as an SR.

By ICs Everything on December 15, 2008
I have a path (reg2out) that initiates in a partition and then goes to top level and, finally, to an output.
So far so good, but the problem is that in the partition spears to have no clock running(the clocks  are defined in the constraint file) for the reg2output path groups, there is no phase shift, just a big external delay and if I put it to zero I am not able to meet timing ( And I am meting timing in the flat design).
This path is a multi cycle path, and I thick that the multi cycle constraints are in the top level partition (It´s a little hard to track this signals because I changed the hierarchic of the design and did partitioning).
Ok, Now that you have and idea of my environment, I have two questions:
What may causing the clock problem in the design?
How can I deal with the multi cycle path problem?
Best regards,

By BobD on December 16, 2008
Hello ICs! This is a pretty tough problem to attempt to solve in a forum like this, but you raise a couple of areas of complexity around partitioning that commonly cause confusing situations to troubleshoot so thanks for leaving this comment.  Have you tried the "justifyBudget" command?  It is targeted as providing enlightenment as to how the tool determined the budgeted values.  Conceptually, the first thing I'd seek to understand is whether at the full-chip level prior to partitioning, which logical clock drives the startpoint and which drives the endpoint.  If they're the same it simplifies things because the timing constraints written for the partition wouldn't necessarily need to create a virtual clock for to associate with the set_output_delay statement on the output pin on the partition. multicycle_paths can get tricky in a hurry for timing budgeting, but the tool should handle them correctly.  I say tricky because in a case where the multicycle path is *selectively* applied to objects that are ultimately driven through the partition pin being budgeted it may be the correct thing to do for the tool to drop the multicycle path. There's some specific information on path-based exceptions in timing budgetng in the SoC-E User's Guide here: sourcelink.cadence.com/.../timingbudgeting.html  Hope this information is helpful!

By ICs Everything on December 17, 2008
Hello BobD!  I just want to say thank you and have I nice week! I Will try it out.
Best regards

By Anand J Stephen on July 21, 2009
nice demo.... is it possible to measure the area inside a module and cutset  after partitoning

By BobD on July 22, 2009
Hi Anand,
There are a couple of different ways the tool gives feedback relative to a module as it's being resized or rectilinear cuts are being introduced.  The first is a "TU%" number that changes as you resize the module.  The second is via the "queryPlaceDensity" command.  For example, in my design I have a partition called 'DTMF_INST/RESULTS_CONV_INST'.  As I resize this partition or introduce rectilinear cuts, the allocated area changes.  It is 62,450 square microns when I ran the command:
encounter 13> queryPlaceDensity
Average module density = 0.593.
Density for module 'DTMF_INST/RESULTS_CONV_INST' = 0.589.
      = stdcell_area 11065 (36807 um^2) / alloc_area 18774 (62450 um^2).
Density for the rest of the design = 0.593.
      = (stdcell_area 29171 (97034 um^2) + block_area 88390 (294019 um^2)) / alloc_area 198114 (659006 um^2).
Pin Density = 0.173.
           = total # of pins 22189 / total Instance area 128626.
Once you've partitioned the design (and the module becomes an instance instead of a hierarchical instance) the area of that partition is best queried by descending and running queryPlaceDensity.
Hope this helps,

By shivaraj on March 14, 2010
Hi,Is this possible to specify a module as partition,which contains only standard cells inside it(i,e there are no hard macros)

By BobD on March 15, 2010
Yes, it is possible to specify a module that has no hard macros within as a partition.  In fact, you can specify an empty module as a partition and I see designers effectively leveraging this approach quite frequently.
A tip in this area: By default the tool doesn't display modules with less than 100 instances.  Try setting this threshold to 0 by going to Tools->Preferences->Display->Min Floorplan Module Size to make empty modules visible.

By shivaraj on March 16, 2010
Bob Thanks alot for the comments...

By shivaraj on March 17, 2010

Is it possible to run cmds setObjFPlanBox/Ploygon or definePartition -corespacing XY coordinates with noninteger multiples of row height..When i ran these cmds with nonint multiples,They are rounded off to int multiples.

By BobD on March 17, 2010
The default behavior is to snap modules to rows vertically.  This preference can be changed via File->Preferences->Floorplan.  Change the "Snap Guides/Regions/Fences to:" from Std Row/M2 pitch to Manufacture Grid, User-defined Grid, or Placement Grid.

By shivaraj on March 17, 2010
Thanks Bob,
with Best Regards

By shivaraj on April 1, 2010
Hi Bob,
Can you please addressthis, if the design is partitioned,If there is a change in one partition how it can be reflected in the top level after committing the partition.

By BobD on April 1, 2010
Have a look at the "assembleDesign" command.  It provides a way to pull together partitions after block-level implementation.

By shivaraj on April 4, 2010
Hi Bob,
Thanks for the reply,
But assembledesign will not keep the pins info.
I mean
1. After partitioning the top level design, if i want to change the location of pins in a partition .How can i change the pin locations in the particular block(partition) and the blocks which have interaction with this  block. and how can i bring this change in to the top level design which has only lef views of blocks(partitions) without affecting the other blocks in the design/with out repartitioning.
2.If any block need to be resized then how it can be done with out affecting the other blocks and how it can be pulled in to the toplevel.
3.If the die size is changed  after power planning and partition,How can i increase the die size without restarting the partitioning.

By Joe on April 3, 2012
Hello Bob,
im facing a rather minor problem. Once i select my module and do "ungroup" (heirarchy down), i do not see my sub modules!!
Please note that they are really small modules (mostly some sort of shift registers! that i must palce all over my NOC).
Any ideas as to how i could view them?

By BobD on May 2, 2012
Hi Joe! If the modules have less than 100 instances you might need to set the parameter described in this blog post: www.cadence.com/.../encounter-puzzler-solution-where-did-my-fences-go.aspx Hope this helps!

By BobD on May 2, 2012
@shivaraj - I'd recommend looking at loadPtnPin, using assembleDesign for just one partition, relative floorplanning, and resizeFPlan for your needs. Tough topics to address quickly but great ideas for future blog posts and discussion.

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