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Custom IC Design Blog

SKILL for the Skilled: Part 9, Many Ways to Sum a List By Jim Newton on May 22, 2013 In the previous postings of SKILL for the Skilled , we've looked at different ways to sum the elements of a list of numbers. In this posting, we'll look at at least one way to NOT sum a list. In my most recent posting , the particular subject... Read More » Comments (0) Filed under: SKILL, Team SKILL, programming, LISP, SKILL++, IC615, summing, sum a list, Jim Newton, SKILL for the Skilled

Virtuosity: 10 Things I Learned in April by Browsing Cadence Online Support By Stacy Whiteman on May 13, 2013 I'll confess: I didn't learn all of this strictly by browsing http://support.cadence.com (Cadence Online Support). I also wandered over onto http://www.cadence.com/community/blogs/ii (Industry Insights blog) and http://www.cadence.com/cadence... Read More » Comments (0) Filed under: Custom IC Design, Virtuoso, mixed signal, AMS, custom/analog, Rapid Adoption Kit, layout-dependent effects, 20nm, Virtuosity

Things You Didn't Know About Virtuoso: Delta Markers in ViVA By Stacy Whiteman on May 9, 2013 This article is dedicated to the gentleman I sat next to at lunch at CDNLive a while back who Is a CAD engineer busily supporting a large user community, but had been stumped by the question "How do I create a delta marker in VIVA?" I'm... Read More » Comments (0) Filed under: Custom IC Design, ViVa-XL, IC 6.1.5, Virtuoso IC6.1.5, Analog Design Environment, Viva, Analog Design Environment, IC615, delta markers

SKILL for the Skilled: Part 8, Many Ways to Sum a List (Closures -- Functions with State) By Jim Newton on April 23, 2013 In the past several postings to this blog, we've looked at various ways to sum a given list of numbers. In this posting I'll present yet another way to do this. This time the technique will be markedly different than the previous ways, and will... Read More » Comments (0) Filed under: SKILL, Team SKILL, programming, LISP, SKILL++, closures, IC615, summing, sum a list, Jim Newton, SKILL for the Skilled, lexical closures

Virtuosity: 10 Things I Learned in March by Browsing Cadence Online Support By Stacy Whiteman on April 11, 2013 Topics in March include advanced analysis in ADE GXL, taking advantage of lots of features for doing statistical analysis in ADE XL, defining bindkeys in ADE L (yes, you can do that!), plus a variety of useful details in the areas of routing and advanced... Read More » Comments (0) Filed under: Custom IC Design, Virtuoso, AMS Simulation, SKILL, Virtuoso Space-based Router, Virtuoso Analog Design Environment, VLS XL, Virtuoso Layout Suite L, VLS GXL, VLS L, Virtuoso Layout Suite XL, Virtuoso Layout Suite GXL, ADE, ADE-XL, ADE-GXL, IC 6.1.5, Monte Carlo, Virtuoso IC6.1.5, Analog Design Environment, modgens, Virtuoso Layout Suite, Analog Design Environment, IC615, Rapid Adoption Kit, RAKs

SKILL for the Skilled: Part 7, Many Ways to Sum a List By Jim Newton on March 25, 2013 In this episode of SKILL for the Skilled I'll introduce a feature of the let primitive that Scheme programmers will find familiar, but other readers may have never seen before. The feature is called named let , and I'll show you how to use it... Read More » Comments (0) Filed under: SKILL, Team SKILL, programming, LISP, SKILL++, IC615, summing, sum a list, Jim Newton, SKILL for the Skilled

Virtuosity: 10 Things I Learned in February By Browsing Cadence Online Support By Stacy Whiteman on March 18, 2013 February was a big month for RAKs (Rapid Adoption Kits)! If you haven't checked out the listings under Resources->Rapid Adoption Kits yet, you're missing out. You'll find databases with detailed instructions, documentation and videos on... Read More » Comments (0) Filed under: Custom IC Design, APS, Virtuoso Analog Design Environment, IC 6.1, Virtuoso Layout Suite GXL, Spectre, advanced node, ADE, ADE-XL, Analog simulation, AMS, IC 6.1.5, Virtuoso IC6.1.5, Analog Design Environment, IC615, variability, Rapid Adoption Kit, RAKs, Virtuoso Advanced Node, Virtuosity

Virtuosity: 10 Things I Learned In January By Browsing Cadence Online Support By Stacy Whiteman on February 15, 2013 This month's highlighted content includes helpful information on wreal modeling, mixed-signal interoperability, verification of digitally-calibrated analog circuits, device and block-level routing and lots more. Enjoy and don't forget to leave... Read More » Comments (0) Filed under: Custom IC Design, Virtuoso, AMS Simulation, Virtuoso Space-based Router, Encounter, mixed signal, ADE-XL, wreal, Analog Design Environment, Rapid Adoption Kit, interoperability, calibration

Things You Didn't Know About Virtuoso: Drag and Drop By Stacy Whiteman on February 13, 2013 I love it when I'm sitting in a meeting with my colleagues or with a group of customers and someone brings up something about our software that they find annoying and another person says "Wait, why are you doing it that way? Why don't you... Read More » Comments (0) Filed under: Custom IC Design, Virtuoso, ViVa-XL, IC 6.1, ADE, ADE-XL, IC 6.1.5, Virtuoso IC6.1.5, Analog Design Environment, Viva, VIrtuoso drag and drop, drag and drop

Introduction to Cadence Virtuoso Advanced Node Design Environment By Hiroshi Ishikawa on January 28, 2013 What can designers do about advanced node technology? This is an introduction to the Cadence Virtuoso Advanced Node design environment, announced Jan. 28, 2013, as a custom/analog design development environment for leading edge-advanced node technology... Read More » Comments (0) Filed under: Custom IC Design, Routing, Placement, analog, advanced node, custom/analog, design flow, STI, module generation, layout-dependent effects, WPE, dynamic coloring, local interconnect, LOD, double patterning, well proximity, LDE, Virtuoso Advanced Node, length of diffusion, 20nm, odd-loop marker, Ishikawa, stress, interconnect layers, analog prototyping, custom

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