Why high yield analysis?
One failed memory cell out of millions cells will cause
the whole memory circuit to fail without ECC (error checking and correction)
techniques. That is why memory designers have high parametric yield requirements
for the SRAM core cell. It requires no fails in hundreds of millions or billions of
brutal force Monte Carlo simulations if foundry statistical models are accurate
up to the high sigma region. Memory circuit
designers also have high yield requirements for other circuit block and memory
partitions, such as sense amplifier sor critical-path partitions.
How to analyze high yield
and debug, improve the design in Virtuoso ADE
Virtuoso Analog Design Environment GXL selects WCD (worst case distance) metric-based method as its high yield solution.
To estimate high yield, ADE GXL will first find the WCD
point in the statistical space. Once the WCD
point is found, the yield can be calculated directly using the WCD.
The accuracy of WCD is impacted by nonlinearity of spec
boundary in statistical spaces. However, that error is not significant in most
high yield applications. The WCD point has the shortest distance from nominal
point to fail region in statistical space. It is also the most probable point to fail in statistical space. During
a continuously running Monte Carlo process, the first failing Monte Carlo point
has a very high probability to be very close to the WCD point in statistical
space. This makes the WCD point very
attractive for creating a high-yield statistical corner because it captures the
circuit condition with the highest probability to fail. This point becomes increasingly important if
designers want to debug and improve the design. Based on the WCD point, Virtuoso ADE GXL provides
the capability to create a high-sigma corner to improve the yield.
The completed high yield solution in Virtuoso ADE GXL is a part of the TSMC AMS
reference flow. It includes:
High yield calculation
Creation of high yield statistical corner
Optimization of the design with high yield corner
Verification of design using high yield calculation
What is coming next? New algorithms
for high dimension!
Cadence R&D co-invented the next-generation high yield
estimation algorithm with researchers from Carnegie Mellon University recently.
The scaled-sigma sampling algorithm works well with high-dimensional nonlinear problems,
which exist in large circuit blocks. Please stay tuned!. The algorithm will be
publicly available in the coming IC616ISR release.
 Shupeng Sun, Xin Li, Hongzhou Liu, Kangsheng Luo and Ben
Gu, "Fast statistical analysis of rare circuit failure events via
scaled-sigma sampling for high-dimensional variation space," IEEE/ACM
International Conference on Computer-Aided Design (ICCAD), pp. 478-485, 2013.