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Virtuosity: 15 Things I Learned in March 2014 by Browsing Cadence Online Support

Comments(0)Filed under: Virtuoso, Analog Design Environment, Variability Aware Design, PVS, ADE GXL

Highlights for this month include lots of useful Physical Verification System (PVS) appnotes and several blog articles on advanced analyses and flows in Analog Design Environment (ADE) GXL.

Application Notes

1. Physical Verification Checks and Generic Tips

Concise overview explaining the basics of the various DRC and LVS checks in rules files.

2. Recommendations and Tips for the PVS DRC Flow

Includes sections on preparation of runsets, running DRC, preparation of design blocks and DRC/LVS check of top-level GDS.

3. Recommendations and Tips for the PVS LVS Flow

Design and runset preparation, links to helpful solutions and sources of common errors.

4. Recommendations and Tips for the PVS Metal Fill Flow

Preparation of runsets, working with different fill scenarios and how to correct errors.

Rapid Adoption Kits

5. Making a layout XL-compliant using Update Binding (XLME)

Uses a sample design scenario to explain how the Update Binding command can be used to increase the VLS XL-compliance of a design using the physical connectivity in the layout and the output from a PVS LVS run. 

6. PSPICE netlist support in ADE

Describes the integration support in Analog Design Environment (ADE) to include a netlist in PSPICE format.

Solutions

7. Why isn't there an hbxf in the Choosing Analyses form?

You have recently started using the GUI for hb analysis and the associated small signal analyses. You noticed that there is a periodic xf (pxf) small signal analysis for pss. Why isn't there a similar analysis (hbxf) for hb?  Click on the link to find out.

8. Is PSF-XL supported for AMS simulation?

(Spoiler Alert) Why yes.  Yes it is.  This solution will tell you how to use this faster analog waveform format. 

9. Why do we have mulitple MMSIM13.1 hotfixes on downloads?

Several MMSIM 13.1 hotfix versions are being maintained on downloads to accommodate specific foundry/PDK rollouts.  Click the link for more information.

10. How to create a form showing a thumbnail image of the cellView

Wow, this could be fun.  A while ago, I wrote an article about how to create thumbnail images.  Now you can find out how to include those images in your own forms.

11. Does bindkey work with forms?

This solution provides an example of how to create a form in which you can register your own set of bindkeys.

12. How to create a custom RAP generator that creates additional constraints?

I would like to modify the existing CurrentMirror generator code to create additional constraints, for example, orientation and matched parameter constraints in addition to the modgen constraint. Here is that sample code.

Blogs

13. Fast Yield and Statistical Corners

Describes the different sampling methods available in ADE XL Monte Carlo analysis, the advantages of using auto-stop if you don't know how many samples are needed, and the types of statistical corners that can be created from the Monte Carlo results to help the designer improve circuit yield.

14. Efficient Design Migration Using Virtuoso Analog Design Environment GXL

The article provides an overview of a methodology for performing process migration for schematics and testbenches, including PDK and design assessment, design migration and final verification.

15. Mismatch Contribution Analysis in Virtuoso Analog Design Environment GXL

When Monte Carlo analysis shows device mismatch variation has become problematic, Virtuoso Analog Design Environment (ADE) GXL Mismatch Contribution Analysis can provide useful diagnostics as a next step. Mismatch Contribution helps in identifying the most important contributors to the variance of the outputs. The article describes the concepts behind this analysis how to use it.

Stacy Whiteman

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