will be under maintenance from Friday, Oct. 3rd at 6pm (PST) thru Sunday, Oct 5th at 11pm (PST). login, registration, community posting and commenting functionalities will be disabled.
Home > Community > Blogs > Custom IC Design > design migration using ade gxl
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Custom IC Design blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Efficient Design Migration Using Virtuoso Analog Design Environment GXL

Comments(0)Filed under: Custom IC Design, Virtuoso, Analog Design Environment, ADE XL, ADE GXL, Design Migration

Requirements for decreased time to market, reduced silicon area, and minimized power consumption move more designs to advanced process nodes.  However, redesign of circuitry is time-consuming, so it is common to migrate existing designs from previous projects, often from one process node to another.  Additionally, migration is also required for:

  • Second sourcing on a similar process from a different foundry
  • Reusing IP in next-generation process nodes
  • Providing variant IPs with different requirements

Migration of analog circuits is often a cumbersome and designer-intensive process.  When migrating a block that has already been designed, verified, and tested to a new process, it is often desirable to maintain the same architecture and in many cases the same or similar circuit performance of the original source design. The following provides an overview of a methodology for performing such a process migration for schematics and testbenches.

Cadence's Virtuoso Design Migration flow consists of:

  • Validation of source circuit performance
  • Schematic migration
  • Assessment of target circuit performance
  • Optimization of target circuit to achieve desired performance

The Virtuoso Design Migration flow is a methodology-driven activity, assisted by automation.There are three major phases - PDK and design assessment, design environment preparation, and design migration and verification.The software used to assist the user is contained within Cadence Virtuoso Analog Design Environment GXL as a part of the optimization tool suite.

PDK and Design Assessment

Before relying on assisted automation, a successful migration requires a careful assessment of both the source and target Process Design Kits (PDKs).  This assessment will help to determine the level of automation that can be applied to the migration or re-design required by determining device correspondence between the source PDK and the target PDK. Once a device correspondence is established, there are several challenges that will determine how well the source design can be migrated. Some of these challenges include symbol compatibility, mapping of passive devices (which can result in fairly large changes in layout area), and design type as this will dictate the level of automation which can be applied during migration. For example, migration of analog blocks function with rail-to-rail voltage margin can be automated significantly more than RF blocks or blocks which are affected by low voltage differences.

Design Migration and Verification

The design migration process starts by replacing the source PDK devices with the mapped devices from the target PDK in each block to be migrated.  This is typically a fairly automated process. The target schematic is then substituted into the testbench schematic. Following migration, the verification plan which was run on the source design is rerun on the target design. The results are compared against the specifications and against the performance of the source design.  If necessary, the block can be optimized to achieve compliance with the specification.

The diagram below outlines a typical front-end migration flow.

A workshop is available which demonstrates this methodology and provides additional details.  You can contact your local Applications Engineer to access this workshop or for additional assistance.


Tom Volden


Leave a Comment

E-mail (will not be published)
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.