Home > Community > Blogs > Custom IC Design > virtuosity xx things i learned in january amp february 2014 by browsing cadence online support
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Custom IC Design blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Virtuosity: 14 Things I Learned in January and February 2014 by Browsing Cadence Online Support

Comments(0)Filed under: Custom IC Design, ADE, ADE-GXL, AMS, Virtuoso Layout Suite, corners, PVT Corners

Time just got away from me last month, so here's two months worth of new content for your browsing enjoyment...

Videos

1. Integration Constraints Capability used in Mixed Signal Design Implementation

Explains and demonstrates the integration constraints capability of the Cadence Mixed-Signal Solution.

2. Virtuoso Floorplanning Design Flow Demo

Demonstrates the Virtuoso Floorplanner Flow: soft and hard blocks, defining cell type attributes, configure physical hierarchy (CPH) – soft block parameters, generate physical hierarchy, block placer, snap pins, editing soft blocks, and pin optimization.

Rapid Adoption Kits

3. Electrically Aware Design (EAD) Workshop

Covers the main functionality of EAD, which is a flow that allows extraction of layout parasitics at any point in the design cycle.  You can resimulate with parasitic effects using layouts that are incomplete.  This flow also supports electromigration analysis based on Spectre simulation results. Includes detailed tutorial and database.

4. IC 6.1.6 Pin To Trunk Device-Level Routing

Steps through the Pin to Trunk Device-Level Routing Flow in Virtuoso in IC6.1.6 ISR4.  This flow enables users to quickly connect device pins in a structured topology.  Includes detailed tutorial and database.

5. IC 6.1.6 Pin To Trunk Block-Level Routing

Steps through the Pin to Trunk Block-Level Routing Flow in Virtuoso in IC6.1.6 ISR4.  This flow enables users to quickly connect block pins in a structured topology.  Includes detailed tutorial and database.

Solutions

6. Fluid Guard Ring Frequently Asked Questions

This is a compilation of the most popular solutions related to fluid guard rings.

7. AMS Designer in ADE FAQ

Answers to customer's most frequently asked questions about the interface to the Virtuoso AMS Designer Simulator in ADE.

8. BindKey Quick Reference in Virtuoso Schematic Editor

A handy chart of all the default bindkeys for the Virtuoso Schematic Editor--single key, Ctrl, Shift and Ctrl-Shift versions, plus function keys--in a concise keyboard layout.

9. bindKey Quick Reference Guide for Virtuoso Layout Editor

A handy chart of all the default bindkeys for the Virtuoso Layout Editor--single key, Ctrl, Shift and Ctrl-Shift versions, plus function keys--in a concise keyboard layout.

10. How to print Monte Carlo statistical parameters greater than 1900 in ADE XL?

A little piece of SKILL code to dump all the values of statistical parameters for each point in a Monte Carlo run to a CSV file.

11. PVS Quick Reference and Frequently Asked Questions

Concise and handy quick reference document on how to use the PVS tools to work with designs, including how to verify a layout against physical design rules and schematics.

Blog Articles

12. Have You Tried the New Transmission Line Library (rfTlineLib)?

An overview of the new RF transmission line library in IC6.1.6 ISR1, which contains wideband-accurate transmission line models in multi-conductor microstrip and stripline configurations.  They are integrated in Virtuoso ADE and accessible from stand-alone Spectre netlists.

13. What Your Circuit Doesn't Know, Can Kill It!

Introduces an upcoming series of articles covering the advanced capabilities of Virtuoso Analog Design Environment GXL to handle variation-aware design issues, such as finding worst-case PVT corners, performing efficient statistical and mismatch analysis, circuit optimization and design migration.

14. What's the Worst That Could Happen?: Worst Case Corners in ADE GXL

This is the first in the above-mentioned series of articles and covers an ADE GXL analysis which enables you to quickly identify the worst case PVT corners for each of your design specifications so you can save time during design iterations and ensure your design is robust.

 

Stacy Whiteman

Comments(0)

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.