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Virtuosity: 15 Things I Learned in December 2013 by Browsing Cadence Online Support

Comments(0)Filed under: Virtuoso, SKILL, Spectre, ADE, ADE-XL, RF simulation, AMS, low power, PCells, Analog Design Environment, layout, PVS

With this month's title, I'll need to start adding the year, as this marks the one-year anniversary of the montly series.  I know it's been a useful monthly exercise for me.  Hopefully it has been helpful for everyone out there as well.

Application Notes

1. How to Utilize a Windowing Technique for Accurate DFT

Explains the best way to set up a transient simulation in ADE in order to achieve good results when performing DFT frequency analysis.  Includes detailed background explanations, comparisons of different methods, and examples.

2. Efficiently Moving Between ADE L and XL in a Sequential Design

Describes an efficient and effective methodology for moving between ADE L and ADE XL in the context of sequentially performing design tasks.  Explains how to move test setups from ADE L to XL, how to set up sweeps, corners and specifications, and the best way to add and manage multiple testbenches.

3. Exchanging OA database views between Encounter (EDI) and Virtuoso (IC)

Basic things to know when interoperating with physical hierarchy between Encounter and Virtuoso.

Videos

4. Using the SKILL IDE in IC 6.1.6

5. Using the PCell IDE in IC 6.1.6

6. SKILL IDE Workspaces and Assistants

A playlist of 3 videos (all accessed from the same link above) explaining how to use the SKILL IDE (Integrated Development Environment) and the PCell IDE, which provide tools and utilities to assist in the creation and debugging of SKILL programs and PCells.

Rapid Adoption Kits

7. PVS Configurator

This is a workshop on how to use the PVS Configurator to create configuration files for PVS technology rules setup.  Using configuration files and letting the designers make choices and save them for subsequent runs is an effective way to provide the options to the designer. Using a configuration file also lets the designers choose options directly from the main rule file supplied by the foundry. Includes detailed instructions and database.

8. Working with the Binder to stay XL compliant

When working in the Layout XL connectivity-aware environment, it is extremely important to establish and maintain the correct correspondence between the schematic and layout instances.  The Layout XL Binder makes and manages this correspondence, allowing the extractor to propagate the correct connectivity through the design.  This RAK explains how the Layout XL Binder works and how the layout engineer can leverage its capabilities to stay XL compliant and increase productivity.  Includes detailed step-by-step examples and database.

Solutions

9. What is the reelaborateonalter option for in Spectre?

Besides being a poster child for why one should use CamelCaseForLongOptionNames, the reelaborateonalter option can save a lot of evalution time in simulation when you have a long list of alter statements between analyses.

10. VerilogAMS wreal vectors and arrays

Nice explanation of how vectors and arrays are defined and handled in VerilogAMS wreal models.

11. PVS Quick Reference and Frequently Asked Questions

I love these Quick Reference/FAQ documents.  Not only do they usually give a quick answer to "how do I do that?", they also have lots of links to other relevant documents and resources.  This one is a concise document on how to use the PVS tools for LVS, DRC, ERC and several other flavors of alphabet soup.  Be sure to download the whole PDF document referenced in the solution to get all the content, including pictures.

12. Packaging Testcase to Send to Cadence: NEW mmsimpack Utility Replaces getSpectreFiles

Solving the problem of "I'm still missing file abc.xyz" when you have to send a testcase to Customer Support, mmsimpack is a new utility to create a compressed tarfile containing all the input files required for an MMSIM testcase.

Blogs

13. Top Cadence YouTube Videos of 2013

Yes, Cadence does have its own YouTube channel.  Sadly, no dancing kittens or adorable puppies (although I confess I didn't look at every single video), but you will find product video demos, customer success stories, and interviews with industry folks and our own Cadence R&D stars.

14. SpectreRF Tutorials and Appnotes... Shhhh... We Have a NEW Best Kept Secret!

This is the latest refresh in a series which is consistently high on Cadence's list of most-viewed blog posts.  Read it.  You know Tawna would never waste your time.

15. Support for Low Power Mixed Signal Designs in Virtuoso Schematic XL

Gives an overview of new capabilities in the Virtuoso Schematic Editor XL to support CPF (Common Power Format) export, import, and verification to improve productivity in a low-power design flow.

 

Stacy Whiteman

 

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