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Virtuosity: 12 Things I Learned in November by Browsing Cadence Online Support

Comments(0)Filed under: Virtuoso, AMS Simulation, EAD, AMS Designer, PVS

New content on a wide variety of topics in November.

Product Information 

1. Cadence Online Support Release Highlights

Find out about all the new improvements which have been made to the Product Pages on COS.

2. PVE Release Mechanism Change Letter

Changes in the way the Physical Verification System (PVS), QRC Extraction and K2 products are released.

Application Notes

3. Troubleshooting connect module issues with the AMS Designer simulator

Describes different types of problems which may be encountered with connect modules in mixed signal/mixed language simulations, and outlines solutions for each.

4. LEF Abstract Generation for IO cells

Describes how to apply the Abstract Generation tool from the Virtuoso IC6.1.5 stream to build optimized LEF abstracts from scratch for use in the rail analysis in Encounter Power Systems.

5. PVS Multi/Distributed Processing

This document provides an introduction, examples, and troubleshooting tips on the job submission process for multi-processing jobs in the Physical Verification System (PVS) tools.

6. How to Identify and Debug Multi-Stamp Errors with Assura

This document helps designers understand the definition of multi-stamp layout errors, what causes them, and how to debug them using the Assura Physical Verification tool.

Videos

7. Extracted View Parameterization

This video demonstrates a new feature in IC 6.1.6 ISR3, which allows you to parameterize extracted or layout/partial layout views in order to perform simulations and optimization to meet design specs, then back-annotate changed and optimized parameter values to the schematic.

Solutions

8. How to arrange assistant tabs on the side

When you stack assistants in Virtuoso, by default the tabs for selecting the stacked assistants appear on the bottom.  This handy feature switches the tabs to the side to make it easier to select the assistant you need.

9. Simulating designs with Out-of-Module references in AMS Designer

This tutorial presents the methods available for reusing a digital testbench that contains an Out-of-Module reference(s) (OOMR) in an analog-mixed signal (AMS) design simulation where SPICE blocks are substituted for some of the digital blocks.  An OOMR is unique in that it is used to reference from one Verilog module to another module and it does not pass through any of the ports. This is very commonly used in purely digital designs. Since this reference does not pass through the ports, special handling is required to make testbenches containing it work in an AMS simulation.

10. ncelab fails with CMINHD, CMINHR, or CMINHE error in INCISV 12.2 ISR

Explains possible scenarios and suggestions for fixing these errors, which can appear in the new release of INCISV due to unconnected inherited connection terminals.

11. Setting up the new Transmission Line workshop library and rfTlineLib

How to find and set up the necessary files and libraries to explore the new TransmissionLineWorkshop and rfTlineLib components.

Blog

12. ICCAD 2013: The New Electrically Aware Design Paradigm

Article discussing a presentation made at ICCAD on Cadence's Electrically Aware Design tools (EAD).   EAD enables design teams to do electrical verification incrementally in real time as each physical layout design decision is made.

 

Stacy Whiteman

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