Home > Community > Blogs > Custom IC Design > virtuosity n things i learned in october by browsing cadence online support
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Custom IC Design blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Virtuosity: 12 Things I Learned in October by Browsing Cadence Online Support

Comments(1)Filed under: Virtuoso Space-based Router, VSR, Routing, Spectre, mixed signal, PAD, AMS, SystemVerilog

Lots of routing, a little AMS, and finishing off with some fun...

Application Notes

1. Constraint Implementation and Validation in interoperability flow

The Mixed Signal Interoperability (MSI) flow allows designers to seamlessly transfer and implement routing constraints from analog to digital designs.  This document covers the steps required to apply and implement routing constraints in Encounter and validate these constraints using the Physical Verification System-Constraint Validation (PVS-CV) utility.

Rapid Adoption Kits

All RAKs include a detailed instructional document and database.

2. Virtuoso Interconnect Routing using VSR

Describes a new use model for running VSR using the Wire Assistant and top-level signal net routing in an analog top-level design.

3. Static and Dynamic Checks

This material describes the usage of the Spectre APS/XPS static and dynamic design checks. These checks may be used to identify typical design problems including high impedance nodes, DC leakage paths, extreme rise and fall times, excessive device currents, setup and hold timing errors, voltage domain issues, or connectivity problems. While the static checks are basic topology checks, the dynamic checks are performed during a Spectre APS/XPS transient simulation.

4. Mixed-Signal Verification -- System Verilog Real Number Modeling

Introduces the new SV-RNM 1800-2012 LRM capabilities that have been made available to aid in mixed-signal verification flows. It provides a basis for the production-level solution that we currently have in Incisive 12.2/ 13.1 that are SV-RNM 1800-2009 LRM centric. Then the RAK introduces the newer capabilities made available by the SV-RNM 1800-2012 LRM that enhance the SV-RNM modeling performance and functionality. The designer will be able to explore the user-defined types and resolution functions along with the debug capabilities made available by SimVision for these new features. Also includes an overview video.

5. Parasitic-Aware Design Using Custom Cells

ADE GXL Parasitic-Aware Design (PAD) features are used to investigate the effect of parasitic devices on a circuit.  RAK has been designed to highlight the features and functionality of the PAD flow in the IC 6.1.6 release, which enable the user to incorporate parasitic estimates into their simulations using custom parasitic elements.  Also includes an appendix on how to build a custom parasitic cell.  This RAK pairs well with the earlier Parasitic-Aware Design Workshop, which covers the entire PAD flow, including parasitic estimation, filtering extracted parasitics, parasitic stitching from extracted views, and parasitic reporting.

Videos

6. AMS Simulation with Multiple Logic Disciplines and Power Supplies on a Single Instance

Demonstrates how to run an AMS simulation with an instance that has multiple logic disciplines and power supplies. In this particular example, the instance has both 1.2V and 3.3V ports.

7. IC 6.1.6 Pin to Trunk Block-Level Routing

Frequent browsers of the Cadence Online Support Video Library may have noticed that many video demonstrations have been organized into "channels" or playlists.  Perfect for binge-watching on a rainy afternoon.  This channel features two videos covering block-level pin-to-trunk routing basics and routing between blocks.

8. IC 6.1.6 Pin To Trunk Device-Level Routing

These three videos cover device-level pin-to-trunk routing basics, wire assistant overrides, routing scope, and via control.

Cadence Community Blogs

9. IC6.1.6 Virtuoso Space-Based Mixed-Signal Router (VSR)

Nice FAQ-style overview of the new features in the Virtuoso Space-Based Router in the context of chip/block assembly routing in mixed-signal analog-on-top (AoT) designs.

10. Spectre XPS -- Cadence Reinvents FastSPICE Simulation

Although it has been under evaluation at several Early Access Partner customers for some months, the official launch of the Spectre XPS FastSPICE simulator was announced in October.  Initially targeted at SRAM characterization, in conjuction with Cadence's Liberate MX tool, Spectre XPS uses advanced partitioning techniques to achieve tremendous performance gains.  

11. EDA Consortium Extravaganza Celebrates 50 Years of Design Automation

"Engineering" and "Extravaganza" are not two words normally seen together, so you've got to gawk a bit when the geeks come out to play.  The 50-year anniversary, and the event, even made it into the Huffington Post, where, no doubt, my mother is still scratching her head wondering "what exactly is it that you do"? 

12. Unhinged

Our new Editor-in-Chief just released Episode 4 of this dynamic, off-the-wall Web show which combines geeky humor with actual news and interesting interviews in a format well-suited to short-attention-span creatures such as myself.  You may laugh, you may cringe, but you will be entertained. 

 

 

 

 

Comments(1)

By cici2013 on November 19, 2013
good !!

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.