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Virtuosity: 16 Things I Learned in September by Browsing Cadence Online Support

Comments(0)Filed under: Custom IC Design, Virtuoso, Virtuoso Analog Design Environment, VLS XL, Virtuoso Layout Suite XL, Routing, ADE-XL, custom/analog, Virtuoso Layout Suite, Analog Design Environment, Schematic Editor, Rapid Adoption Kit, Virtuosity, pin placement, layout


Rapid Adoption Kits

By now, I think you know what RAKs are, and that they include a detailed instructional document and database.  Use the title link above to access the main landing page and browse all the available material.

1. DRD-based Interactive Compactor

The DRD-based interactive compactor can help you change the spacing between existing objects in your layout either through compaction or spreading. It can also fix spacing violations between shapes in your layout.

2. FastXOR

PVS XOR is a widely and highly needed application by designers to compare their layout databases.

3. IC 6.1.6 Crosstalk

This kit outlines a strategy for crosstalk prevention during both interactive and automated routing, using Virtuoso constraints.

4. PVS Interactive Short Locator

This is a workshop on the PVS Interactive Short Locator Application. This is designed to help new users learn and use the LVS shorts debugging feature more effectively.

5. Stamping Conflict Debugging in LVSDE

Resolving Stamping Conflicts has remained an area of challenge for the designers and the Stamping Conflict Debugger has been aimed at easing this process. This RAK is a workshop on the Stamping Conflict Debugger to help new users learn and use this feature more effectively.

6. IC 6.1.6 Pin to Trunk Block-Level Routing

This material steps through the Pin to Trunk Block-Level Routing Flow in Virtuoso in IC 6.1.6. The objective of this flow is to increase layout productivity through improved routing functionality aimed at block-level interconnects. This flow enables users to quickly connect block pins in a structured topology.

7. IC 6.1.6 Pin to Trunk Device-Level Routing

This material steps through the Pin to Trunk Device-Level Routing Flow in Virtuoso in IC 6.1.6. The objective of this flow is to increase layout productivity through improved routing functionality aimed at device-level interconnect. This flow enables users to quickly connect device pins in a structured topology.


8. Using amsDmv To Complement ADE XL Spec Comparision Form

This video highlights several very useful, but under-utilized aspects of the Custom IC tool suite--using ADE XL Spec Comparison to compare measured results, using amsDMV to compare waveforms and using amsDmv as a simulation cockpit to analyze small design changes.

9. Physical Verification System: Debugging DRC Results

This video is intended for new PVS users to help them quickly understand how to analyze and debug the PVS DRC run results using the DRC Debug Environment.

Application Notes

10. PVS Bindings by Name during PVS LVS Run

This document talks about the default PVS behavior around binding cells and pins across layout and schematic as well as discusses various commands to control the binding behavior, mostly using a question and answer style.

11. Circuit Prospector in Virtuoso (IC 6.1.5/6.1.6): An Overview

The Circuit Prospector is another under-utilized Virtuoso feature which can help identify structures and objects in a schematic with important electrical or topological characteristics.  This document provides a guide to setup, usage an customization of this Assistant.


12. FAQ: Tips for Using S-Parameters in Spectre and SpectreRF

A great collection of tips and articles on using s-parameters in Spectre and SpectreRF.  Also, check out Tawna's library of useful blog articles in the RF space.

13. SKILL examples of forms, fields and menus

Everything you always wanted to know about creating forms and menus in SKILL, with example database and code.

14. Is there a way to run Mark Net in a user defined area of the design?

Why, yes.  Yes there is.

15. Virtuoso Layout Editor: Change color of the ruler - New Environment Variable

16. Pin Placer verses (sic) Pin Optimizer, which one to use and when?

This solution explains the difference between the 2 pin placement engines in VLS XL and provides guidelines for which one to use and when.


Stacy Whiteman 


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