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Virtuosity: 10 Things I Learned in February By Browsing Cadence Online Support

Comments(0)Filed under: Custom IC Design, APS, Virtuoso Analog Design Environment, IC 6.1, Virtuoso Layout Suite GXL, Spectre, advanced node, ADE, ADE-XL, Analog simulation, AMS, IC 6.1.5, Virtuoso IC6.1.5, Analog Design Environment, IC615, variability, Rapid Adoption Kit, RAKs, Virtuoso Advanced Node, Virtuosity

February was a big month for RAKs (Rapid Adoption Kits)!  If you haven't checked out the listings under Resources->Rapid Adoption Kits yet, you're missing out.  You'll find databases with detailed instructions, documentation and videos on many tools, features and flows.   They've become very popular and we're adding more all the time.

We're also featuring content on routing, schematic PCells, ADE XL job distribution, advanced node layout techniques and a new course on high-performance circuit simulation.

Rapid Adoption Kits

1. Creating Custom Connect Rules for AMS Simulation in ADE

Outlines the process used to create custom connect rules for mixed-signal simulation in ADE using AMS Designer.  Includes a database example and step-by-step manual.

2. Spectre Device Checks

Describes the usage of the Spectre device checking feature.  Spectre device checking is used to monitor if devices in your circuit are violating user-defined conditions.  For example, checking to insure that low voltage devices are not inadvertently used in high voltage conditions.  Checks can show warnings or cause the simulation to stop on an error.  This is a very powerful feature, but can be somewhat confusing to set up, so this database and step-by-step manual will be extremely useful.

3. Using Spectre Save-Recover

Spectre and Spectre Accelerated Parallel Simulator (APS) have the capability to save a simulation state and restart the simulation from the saved state file. The simulation state for long simulations can be periodically saved to allow recovery from unforeseen circumstances, such as power outages or disk full issues. The save/recover methodology can also be used to restart simulations with different parameters or inputs. This example will illustrate using Spectre/APS Save-Recover from both ADE and command line based simulation.  Includes database and detailed manual.

4. Basics of Inherited Connections

Often times in design, the same cells need to be used in different parts of the circuit that use different power supply voltages. Inherited connections provide a mechanism to selectively override net connections by placing properties on the parent instance. Therefore the same cell can be used with different power supplies without the need for explicit power and ground pins. This document describes how inherited connections work with a sample design which shows how power and ground connections for the same cell can be different in the schematic hierarchy.   It also outlines the process used to resolve inherited connections.  Includes an example database.

5. Passing Parameters in the Schematic Hierarchy with pPar

Schematics can be parameterized with pPar parameters to allow passing parameters from a parent instance to the lower level schematic (the child). This mechanism facilitates defining high level parameters to define the functionality of the circuit.  Includes database and detailed manual.

Application Notes

6. ADE XL Job Policy Setup

This document (and the complementary ADE XL Simulation Flow document) are essential to getting the most out of the powerful job distribution capabilities in ADE XL.  You'll learn about the different types of job distribution available, their options, how they work and how to set them up.


7. How to set non-uniform Routing Tracks with IC6.1.5 VSR-RIDE and do routing

For IC6.1.5 users who wish to do gridded track based routing, this document will demonstrate how to set up the Tcl/tk commands in a script that can be run within Virtuoso Layout GXL or through the Routing Integrated Development Environment (RIDE).  Tracks can be setup for all routing layers of just selected routing layers.

8. Schematic PCell Example with inherited connection.  netExpression added to wire and label display

Includes sample SKILL code and testcase database to create a schematic PCell with inherited connections.

9. How to enable the color engine in ICADV12.1 and later versions like upcoming IC6.1.6

The Virtuoso Layout environment for advanced node design includes features to support metal coloring for double-patterning technologies.  This solution shows you how to enable those features.

Course Announcement

10. High-Performance Simulation using Spectre Simulators v12.1

In this course, you use the enhanced technologies of Virtuoso Spectre Circuit Simulator, including the Accelerated Parallel Simulator (APS), to run fast and accurate analog simulations on large, complex, mixed-signal designs providing a significant performance gain over baseline Spectre simulation.

You explore the use of multithreading options, APS, Fast APS and APS in distributed mode. You verify the circuit performance and identify the potential failure modes by running dynamic checks with Spectre and APS and then examine the results by viewing the appropriate XML file. You run Spectre APS stitching of DSPF, SPEF, and DPF files and a postlayout simulation. You run high-capacity EMIR simulation using Spectre APS.

Stacy Whiteman




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