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Virtuosity: 10 Things I Learned In January By Browsing Cadence Online Support

Comments(0)Filed under: Custom IC Design, Virtuoso, AMS Simulation, Virtuoso Space-based Router, Encounter, mixed signal, ADE-XL, wreal, Analog Design Environment, Rapid Adoption Kit, interoperability, calibration

This month's highlighted content includes helpful information on wreal modeling, mixed-signal interoperability, verification of digitally-calibrated analog circuits, device and block-level routing and lots more.

Enjoy and don't forget to leave feedback at the top of the individual content pages in COS (Cadence Online Support) to let us know what information you find most useful.

Rapid Adoption Kits

1. Guidelines on Modeling Analog Circuits with wreal

This material illustrates wreal modeling concepts by migrating a Verilog-A based model of an AM modulation-demodulation system to a wreal model with Verilog-AMS. The wreal equivalent of each block is created to build up an all digital simulation for the system.  Guideline steps for creating wreal Verilog-AMS models are developed and used for developing the wreal models.  The RAK includes a workshop database and detailed manual.

2. IC6.1.5 VSR (Virtuoso Space-based Router) Workshop

This workshop highlights interactive, assisted and automatic routing features available in Virtuoso Space-based Router (VSR). During the course of the workshop you will be able to apply these features to do some device and block level routing and analyze your results in R-IDE (Routing Integrated Development Environment).  The RAK includes a workshop database and detailed manual.

Application Notes

3. AMS Designer INCISIVE Command-line Flow Use Model

This document provides an overview of how to run mixed-signal simulations from the command-line interface of the AMS Designer simulator using the "irun" command.  It includes information on setup files, options, command syntax and mixed-language specifics, as well as examples and pointers to the workshop database and other references.

4. Calibrated Verification with ADE XL

This document focuses on a topic about which I am frequently asked by customers--how to use ADE XL to verify digitally calibrated high-performance circuits.  It covers the details of the ADE XL features supporting this technique, including the use of calcVal expressions and pre-run Ocean scripts.  Detailed worked examples are given, complete with accompanying database.

5. Open Access Reference Library Import

Recommendations on how to import a standard cell or IP reference library for use in OpenAccess mixed-signal design using the Incremental Technology Database (ITDB) and LEF Import.

6. ADE XL Quick Start

Given that the ADE XL User Guide is now 846 pages, this document is intended as a quick reference tutorial in using the basic functionality in ADE XL, including setting up tests, running simulations, basic post-processing, sweeps and corners. 


7. New AHDL Linter in AMS Designer 12.2

Detailed information on how to use the AHDL linter feature in AMS Designer which enables you to detect modeling issues in Verilog-A and VerilogAMS (AHDL)  languages.

8. Virtuoso Encounter Mixed-Signal Flow: Quick Reference to Basics and Most Referred Solutions

This is a concise and handy reference document for using Virtuoso and Encounter to manage mixed-signal design flows that allow the mixing of digital and analog content throughout the design hierarchy.  It includes information on design and technology data requirements, environmental configuration and an extensive list of links to helpful solutions, reference documents and application notes.


9. Cadence Chemical Mechanical Polishing (CMP) Predictor - An Introduction

An introduction to the Cadence Chemical Mechanical Polishing Predictor.  It also describes the extraction process, simulation flow and steps to monitor the job status and view extraction results.


10. Introduction to Cadence Virtuoso Advanced Node Design Environment

An introduction to the new features that are available in Cadence's Virtuoso Advanced Node design environment which support the complex requirements inherent in advanced process technologies at 22nm and below.

Stacy Whiteman



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