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Introduction to Cadence Virtuoso Advanced Node Design Environment

Comments(0)Filed under: Custom IC Design, Routing, Placement, analog, advanced node, custom/analog, design flow, STI, module generation, layout-dependent effects, WPE, dynamic coloring, local interconnect, LOD, double patterning, well proximity, LDE, Virtuoso Advanced Node, length of diffusion, 20nm, odd-loop marker, Ishikawa, stress, interconnect layers, analog prototyping, custom

What can designers do about advanced node technology? This is an introduction to the Cadence Virtuoso Advanced Node design environment, announced Jan. 28, 2013, as a custom/analog design development environment for leading edge-advanced node technology.

Problems of Advanced Node Design

When designing with the most advanced node technologies including 22nm technology and beyond, you will encounter many new problems that no one could have anticipated from previous design work.  New tools in the design flow need not require a completely new design flow.  You should maximize the effectiveness of the current design environment.  Then, you need to handle new problems appropriately and accordingly.

Generally speaking, you will need to pay special attention to the following things with advanced node design.

  • Multiple Patterning
  • Layout Dependent Effects (LDE)

o Length Of Diffusion (LOD) / STI Stress
o Well Proximity Effect
o Interconnect R, C, and inductance

  • Use of Local Interconnect Layers


Fig 1 (a) Length Of Diffusion (LOD)         

Fig 1 (b) Interconnect layers

Fig 1 (c) WPE (Well Proximity Effects)

Fig 1(c) shows the WPE (Well Proximity Effect), one of the LDEs. The performance of the devices is different for 26db (~12x) depending on the placement locations of the devices from the edge of the well.

For advanced node design, those problems must be evaluated and considered in the design flow.

Current Design Flow

The current generic design flow that is mainly used for the 45nm and 32nm process nodes is shown in the following Fig 2. The current design flow represents the collected wisdom of many designers over many development processes. Indeed there is a big advantage of the current design flow because the designer has been familiar with it for a long time.

However, it is also true that the flow has the limitations listed below.

  • Each step is connected serially. When some steps have problems, many undesired iterations will be induced.
  • Automation is not used to its full potential.
  • Additional and incremental analysis during the design is not easy.
  • Hidden problems in the design including performance variance affected by LDE can go undetected until a very late phase in the design process.

The problems in the advanced nodes listed above all occurred with the previous technology, too. However, the reason that the current (existing) flow that is like the flow shown in Fig 2 is that the effects of those problems in the previous process technologies were very small, and they could be ignored. In the advanced technology required for 20nm or 14nm designs, those problems cannot be ignored. Therefore, the design process cannot be concluded unless designers detect these problems at an early stage of the design, and take necessary actions.

Also, the architectures of double patterning and Interconnect layers have already emerged in the previous technologies. However, these architectures will make a huge impact on performances of designs in advanced node technology. The design process itself needs to be re-evaluated for the advanced node design.

Fig 2. Current generic design flow

Therefore, an ideal design environment for advanced node technology is a design flow that allows the user to detect and resolve the non-ignorable problems in advanced node technology without invalidating the usability of the current design flow.

Cadence's design flow for advanced node technology

Fig 3 shows the design flow realized by Cadence Virtuoso Advanced Node design environment.

Fig 3. Cadence Virtuoso Advanced Node design environment for advanced node technology

At first, this flow does not require the user to change his current design flow. It has various enhancements for advanced node technology and inherits properties of the familiar, current design flow.

Several enhancements for advanced node technology are introduced below.

Analog Prototyping Step

In this step, the user can perform a simulation and consider the LDE before starting the actual layout. This is realized by prototyping the device layout, and simulating the design while considering LDE parameters. With this step, one can dramatically reduce the design modification work caused by performance gaps between the actual design after place and route is completed, and the initial simulation result.

It will work most effectively for considering the WPE (Well Proximity Effect) and performance effects caused by physical stress of the STI (Shallow Trench Isolation).

This step is very powerful because it not only shows LDE effects in a window, but it also allows the user to quickly check and verify characteristic changes due to LDE by running a simulation.

The following figure (Fig 4) shows this part of the step (Analog Prototyping).

Fig 4. Analog Prototyping

Module generation, Device placement Step

In the real design generation phase, the user can generate modules using Modgen and can place devices using the newly enhanced Pcells.  Device placement work in advanced node technology is like pulling teeth.  Very complex and rigid design rules need to be satisfied.  Fig 5 shows sample complex-design rules related to the device placement.  To effectively support those complex design rules, the Pcell abutment function in Cadence Virtuoso Advanced Node design environment was dramatically enhanced.  The Pcell abutment function evaluates the relationship between the device to be placed and adjacent devices and realizes the best placements of devices automatically.

Fig 5. Example of complex device placement

Routing step

Routing work on the Local Interconnect Layer (LI) differs dramatically from the routing on the other routing layers.  As the figure (Fig 6) shows, the LI layers exist between Metal1 and base layers.   The layers allow contact-free connection.  Also, the length and width of wires on the LI layers are tightly specified.  The layers have very rigid constraints.



Fig 6. Local Interconnect Layers

In Cadence Virtuoso Advanced Node design environment, the user interface has been enhanced as well as the technology file so that the user can smoothly work on routing wires on the local interconnect layers (Fig 7).

Fig 7. Routing Environment for Local Interconnect Layers

Also, the DPT Assistant (Fig 8) can be used in Cadence Virtuoso Advanced Node design environment so that the routing can easily be done when considering double patterning architecture.  The DPT Assistant immediately informs the user where in a design that double patterning conflict occurs.


Fig 8.  Dynamic Coloring Assistant

Fig 9 shows the Odd-Loop Error Detection done by Virtuoso Integrated PVS (IPVS).  In Cadence Virtuoso Advanced Node design environment, PVS, a sign-off level Design Rule Checker is fully integrated.  It performs "Dynamic Signoff Checking" when a design is updated.

Fig 9. Odd-loop error detection


This document has been a quick introduction to new features that are available in Cadence's design development environment for advanced technology.  The Cadence Virtuoso Advanced Node design environment is the brand-new design environment that not only supports each new requirement but also integrates new steps into the existing design flow without needlessly disrupting that flow.

Also, the biggest and hidden advantage of this design flow is that software will obviate the possible design problems inherent in advanced node design even if the designer is unaware of these new problems.  As the result, the flow can minimize undesired iteration in the design process that was the limitation of the previous design flow.  This "Correct-by-Construction" approach realized by Cadence Virtuoso Advanced Node design environment can dramatically reduce the entire design turnaround time.

Hiroshi Ishikawi


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