Although many automatic layout generation tools are available to automate design creation, the layout modification/correction step (fixing design rule violations) is not automated very well. Consequently, design modification including error correction typically needs to be done manually.
A good solution to automate the layout modification/correction step can be provided by a layout optimization tool that optimizes the areas containing design rule violations in a layout, and fixes the violations automatically. Such a capability is provided by the Interactive Design violation Fixing (IDF) tool that was first provided in the Virtuoso IC6.1.4 release.
The primary advantages of IDF are:
1. Only required areas are modified and corrected (nothing will be changed outside of the selected areas.)
2. It can be called any time in any design phase (even if the layout has not been finalized.)
3. Quality of the modified layout is stable (the results won't vary according to engineers' experience or design manner.)
As the first step to realize the above requirements, IDF was implemented in our IC6.1.4 software release by freezing (not changing) details outside of specified areas. (Fig 1)
Fig 1. IDF- IC6.1.4 (freeze outside of the area to be optimized)
Although the IDF in IC6.1.4 worked very well, freezing areas around the area to be optimized had the following two limitations:
1. It takes long time when a design is big because the entire layout data needs to be loaded on the dynamic memory.
2. When multiple areas are selected, one optimization failure ("infeasible") causes the optimization failure of all selected areas. (All areas must be optimized at the same time since optimizing a design means generating a result that satisfies all requirements simultaneously.)
Therefore, IDF needed to be enhanced so that automated layout modification/correction worked regardless of the design size, and without infeasible results interrupting the flow. In the latest release, IC6.1.5, the IDF has successfully been enhanced to realize the above requirements.The solution to the problem is applying the automated correction (IDF) only to the affected region. The areas to be optimized from a design are extracted. Then, the extracted areas are sent to the IDF engine one by one (Fig. 2)
Fig 2. IDF in IC6.1.5
IDF works very fast in most cases because the size of the data is very small. The following table compares benchmark results of IDF in IC6.1.4 and in IC6.1.5. IDF in IC6.1.5 finishes all error fixing within 1 minute.
Table 1. Runtime comparison (Frozen Donut Area vs. Area Segmenting Method)
|Size (um x um)||# of Design Rule Errors ||IDF in IC6.1.4||IDF in IC6.1.5|
|Stdcell DLY1X4 ||4.06x2.61||1||2s||0.5s|
|CustomDigital 1||15 x 15||7||3min 52s||4s|
|Analog 2||4.5 x 6.5||8||4s||1s|
|Analog PLL||650 x 550||30||> 2hours *1)||30s *2)|
*1) Job was terminated during constraint generation phase.
*2) 2 Infeasible results were reported.
Runtime (User time) was measured.
VMWare Virtual Machine
Redhat Linux 4
RAM: 1 GB
Dell Laptop PC M65
CPU :Intel Core 2 CPU 2.16GHz
RAM : 3.25 GB
OS Windows XP SP3
Figure 3 shows the biggest design used for this benchmark test.
Fig. 3 Analog PLL design 650um X 550um（# of DRC Errors 30 -> 2 : runtime = 30sec)
This approach (loading only the specified area) allows the following benefits:
- No design size limitations
- Very fast
- Non-stop optimization despite some infeasible results
IDF in IC6.1.5 works effectively for medium / large designs. It can also handle designs of chip-level complexity. Because each optimization task is discrete, the flow does not become interrupted by an infeasible result error. Also, the runtime is very fast, since the size of each extracted cell tends to be small.
Actually, IDF in IC6.1.5 consists of multiple small IDF fixes in IC6.1.4. Because a huge amount of design time is wasted on inefficient manual modifications, IDF in IC6.1.5 is a great solution to correct errors. IDF in IC6.1.5 is the answer to industry’s demand for automatic error correction.
Sr. Engineering Manager, Physical Design
San Jose R&D, Custom IC, Silicon Realization Group