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Will Evolving Language Standards Address Mixed-Signal Verification Problems?

Comments(0)Filed under: analog, mixed-signal, mixed signal, ADE, SVA, AMS, SystemVerilog, assertion-based, accellera, DMS, SV-DC, A-SVA

Mixed-signal verification has been one of the hottest topics in the past year, and it was very evident in DVCon 2011, looking at the number of technical papers submitted on this topic. Engineers are looking for solutions to solve tough problems in this space, and the creativity put into developing custom solutions is mind blowing. We are at an interesting stage where engineer's minds are racing past the capabilities of EDA tools and the lack of standard languages to find their own innovative solutions.

First generation standards such as Verilog-AMS and Verilog-A introduced behavioral modeling to the analog world. But the complexity of mixed-signal designs have grown exponentially, and this begs for the evolution of next generation standards. Some of the successful methodologies adopted for digital SoC verification need to be extended to the analog/mixed-signal world. Extraordinary work is being done developing these new standards under the leadership of Scott Little from Freescale Semiconductor, chair of the IEEE SystemVerilog Discrete Real Modeling Committee (SV-DC) and Analog SystemVerilog Assertion (A-SVA) committees. Scott was grateful to address some of my questions on the progress of these standards committees.

What is the charter of SV-DC?  How can one participate or contribute to this effort?

SV-DC intends to provide capabilities in SystemVerilog to support efficient modeling of analog/mixed-signal circuit components.  These models are to be simulated by the event-driven simulation engine and should, therefore, exhibit simulation performance comparable to digital models and be suitable for system level simulation.  The new modeling capabilities will be achieved by natural extensions to the existing SystemVerilog language; no analog solvers or netlist manipulations will be required.  [Note: This is the Executive Summary from the SV-DC roadmap.  The entire roadmap can be found at http://bit.ly/apjS6s]

SV-DC is a technical subcommittee of the IEEE P1800 (SystemVerilog) Working Group.  The participation rules for this group have recently changed.  The current rules state that IEEE SA Advanced and Basic members can participate as observers.  For a list of IEEE SA members please see http://standards.ieee.org/develop/corpchan/mbrs1.html.  For active participation IEEE-SA advanced member companies need to join the P1800 Working Group which requires an additional fee.  Information regarding those fees can be obtained from the P1800 Working Group chair, Karen Pieper (karen_l_pieper@yahoo.com).

What applications do you see for the SV-DC functionality?

The primary application that I see for the functionality being developed in SV-DC is the modeling of AMS circuits.  Modeling experts and SoC verification engineers have an increasing need for efficient, abstract models for AMS components.  The features being discussed in SV-DC will help them fill this need.

Can you tell us about the progress rate of SV-DC?  When can we expect a final standard?

The SV-DC committee is currently in the process of refining a proposal that adds user-defined nets and resolution functions to the SystemVerilog language.  We believe this proposal provides a core set of real-valued modeling features in SystemVerilog.  For example, using these features a user can create a single net containing two real values, one representing voltage and the other representing resistance.  In cases where there are multiple drivers on a net of this type the user-defined resolution function will be used to determine the resolved value of the net.

We are on schedule to vote on a final version of that proposal in early May.  After that proposal is complete, we have until October 1, 2011 to address additional items.  The next item on our agenda is not currently set.

This work is expected to be in the next revision of SystemVerilog which is currently scheduled to be released in the middle of 2012.

Why was this done in IEEE Vs Accellera?

The user community wanted a real-valued modeling solution in the SystemVerilog language, and SystemVerilog work is done in IEEE.  It may have been possible to add these features to SystemVerilog through the SystemVerilog/Verilog-AMS (SV-AMS) merger, but it was felt that the majority of the desired features are not present in the current Verilog-AMS standard and would require significant changes to the core SystemVerilog functionality.  Based on that analysis, it was decided to add these features directly to the SystemVerilog standard while managing any potential compatibility issues with Verilog-AMS wreal.

Will SV-DC make SV-AMS irrelevant? What things should SV-AMS deliver that SV-DC cannot?

No, SV-DC will not make SV-AMS irrelevant.  SV-AMS brings the promise of being able to mix Verilog-AMS constructs with SystemVerilog constructs.  For example, using SV-AMS I could access electrical quantities or analog events in an assertion.  I could connect a driver to an AMS DUT using an interface.  These constructs provide tremendous value and are clearly outside the SV-DC charter.

What is the charter of A-SVA? How can one participate or contribute to this effort?

A-SVA is a subcommittee of Verilog-AMS that is charged with studying language features necessary for AMS assertions.  To participate one only needs to begin attending the meetings or participating on the e-mail reflector.  Instructions for joining the e-mail reflector can be found on the ASVA web page at http://www.eda.org/twiki/bin/view.cgi/VerilogAMS/AmsAssertions

Where does A-SVA fit in? Is it designed to be part of SV-AMS?

A-SVA fits best into SV-AMS.  The A-SVA committee spent a number of months trying to fit the A-SVA requirements into Verilog-AMS or SystemVerilog alone.  The eventual conclusion was that the full power of SV-VAMS is needed to properly support A-SVA.  The committee is currently investigating the addition of unclocked LTL operators into SVAs as well as the addition of SVAs to Verilog-AMS.  Both of these efforts are useful, but they will not provide the full power of A-SVA originally envisioned by the committee.

What are the technical challenges extending assertions from digital to analog/mixed-signal?

One of the primary challenges in extending assertions from digital to AMS is efficiently managing the notion of dense time.  The assertion evaluation engine will not be efficient if it checks the property at every point of time.  However, it must check often enough to accurately measure the property.

Another key difficulty is defining the syntax and semantics for an assertion language that allows the free intermingling of realtime and clocked sequences and properties.  We believe this is a key feature of a user friendly AMS assertion language, but it is a difficult problem to solve.

What is the value add of assertions for verifying analog designs?

The value added by assertions when verifying analog designs is very similar to the value added by assertions when verifying digital designs.  Assertions enable designers and verification engineers to encode assumptions and specifications in an unambiguous manner.  Assertions also enable efficient debugging by identifying errors when and where they occur.

What needs to happen for engineers to adopt such a methodology?

I believe the primary thing that needs to happen for adoption of an AMS assertion-based verification methodology is tool support.  Right now, I am seeing some adoption of the methodology even with the convoluted ways we are forced to use it today.  I expect increased adoption when the flow becomes easier to use.  Increasing adoption of these methods isn't difficult when you can demonstrate that it finds bugs and improves quality.

Do you think a "metric driven verification" methodology can increase the overall productivity of analog designs? Why?

I hesitate to say that metric driven verification will increase the productivity of analog designs.  I would rather focus on how it can improve the quality of analog design.  Metric driven verification is focused on quantifying what has been verified and what still needs to be verified.  I believe that adding this additional structure into the traditional AMS verification process will improve the overall quality of AMS designs.

What are the main drivers for adoption of such a methodology?

The main driver is avoiding the dreaded re-spin.  AMS circuits are becoming more complicated along several different axes.  Two of the most notable drivers of metric driven verification are the addition of complicated digital control and low power features.  Traditional analog verification methods do a good job of getting the analog content functioning properly, but they often fall short in dealing with problems related to integration and low power features.  I have seen a metric driven methodology improve the ability for AMS designers to identify and fix integration and low power issues.

Srikanth V Raghavan

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