Decreasing geometries and increasing design complexity are
making the task of designing custom ICs very difficult (not that it was easy
before). One of the main issues designers grapple with is the issue of
parasitics and their effect on design specifications and yield estimates. With increasing cost pressures and decreasing
ASPs, meeting yield targets could decide the commercial success of the chip.
In an era of ever shortening design cycles, waiting for
layout engineers to provide designers with a complete, optimized layout and
then perform post-layout verification is not always preferable, and in many
cases it's inefficient. Having a methodology to consider the effects of parasitics in
the early stages of design cycle is crucial to the success of the project. This
is precisely where a parasitic-aware design flow comes to the help of designers. Parasitic-aware design is a design
methodology that allows designers to understand and analyze the effect of
parasitics and help take corrective actions.
There are two aspects to parasitic-aware design flow. One
part of parasitic-aware design deals with the front-end design, and the other
with the physical implementation (see parasitic-aware design flow diagram here). In this blog we will focus on design and verification
phases of design, cover important features of parasitic-aware design flow, and show how
these features add value to designers in their day-to-day design activities.
In the front-end, the industry leading tools such as the Virtuoso
Schematic Editor and Virtuoso Analog Design Environment allow designers to
capture design intent and characterize the design for a multitude of operating
conditions. A schematic editor with features like Canvas Magnifier, Custom Checks
Creator, and HTML Publisher for Schematics will ensure reduced mouse clicks and
increased productivity. Analog Design
Environment XL’s Multi-Test environment has statistical analysis (Corners, Monte
Carlo) capabilities that allow designers to use hardware resources efficiently,
and comprehensively verify the design.
Native RelXpert integration with Analog
Design Environment XL will enable designers to perform reliability analysis and
better understand age and stress related effects on their designs. Design
documentation capabilities provide designers with a simple but powerful way to capture
all the necessary information and electronically tie this information to the IP
for improved intra- and inter- design team communication.
Parasitic estimation and parasitic stitching to incorporate
parasitics in early stages of the design are key steps in the parasitic-aware
design flow. These techniques enable
designers to leverage the prior knowledge and experience they have about
parasitics on similar designs, and to incorporate this knowledge into the design
they are working on. Analog Design Environment GXL provides designers with an easy
to use GUI to accomplish this task. Designers
can estimate parasitics by manually adding R, C, L and K to the schematic, such
that the estimated parasitics are representative of those coming from the final
Alternatively, users can stitch parasitics from previously designed
modules into the design they are working on. Since the majority of the designs
are reused in one form or another, parasitic stitching could be a more accurate
form of parasitic estimation. Designers can then use Analog Design Environment XL
to simulate and compare results with schematic design to analyze and understand
parasitic effects. Designers can subsequently filter, refine, and customize
these parasitics to meet their design specific needs and analyze their effects
on various figures of merit.
Designers can iterate through this process
multiple times to clearly understand parasitic effects in the early stages of
design cycle, and do so without a final layout.
The availability of various Cadence simulators (such as Spectre, SpectreRF, UltraSim, Accelerated Parallel Simulator, AMS
Designer), all using common device models, seamlessly integrated into a single
GUI, give designers freedom to choose simulation tools that meet their
accuracy, capacity and performance needs. Finally, designers can take advantage
of Analog Design Environment GXL optimization to take corrective action and
optimize their designs to mitigate parasitic effects.
NOTE: To access
“Quick Start” videos that show step-by-step instructions on how to accomplish
various tasks outlined above, please contact your local AE or Sales Engineer.
In summary, the parasitic-aware design flow is not a panacea for
all the parasitic issues that are plaguing your design, nor is it a single tool
that is going to perform miracles. Parasitic-aware design, on the other hand,
is a design methodology that allows designers to systematically analyze and understand
effects of parasitics during early stages of design cycle and help take
Since designers know more about their designs than anyone
else, parasitic-aware design provides a consistent methodology to capture this
knowledge in a systematic way, helping designers to maintain design intent
throughout the design process. By providing designers with a faster and better
way to bring parasitics back into the design, parasitic-aware design allows
designers to avoid over-designing and instead focus their energies on fine
tuning their design to increase the yield.