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Virtuoso IC6.1.5: Software and Fine Red Wine

Comments(0)Filed under: Custom IC Design, Virtuoso, DFM, Constraint-driven, analog, mixed-signal, mixed signal, Analog simulation, parasitics, AMS, IC 6.1.5, Virtuoso IC6.1.5, parasitic-aware design, custom/analog, low power

Software, like fine red wine, can get better with age as well -- but it requires constant advancements to remain a vibrant contributor.  Such is the case with the Virtuoso IC6.1.5 custom/analog technology release, which delivers on the promise of Silicon Realization with capabilities that maintain design intent throughout the custom/analog flow, simplify the abstraction of analog information to provide high-performance verification capability, and lead to design convergence by providing a common cockpit for in-design signoff technology and support for the Cadence Low-Power Solution.

The enhanced Virtuoso-based custom/analog flow spans design, implementation and verification. The amount of individual tool updates are too numerous to blog about, so I encourage our users to spend a bit of time with the What's New document that is available from  Cadence Online Support.  Instead, I want to highlight and provide more details on the three larger elements that are encapsulated in the IC6.1.5 release.

Support for Globalized Teams:  A variety of new publishing features within the schematic, analysis environment, and waveform window allow for the easy exchange of information across the web.  We realize that many of our customers work on a 24-hour clock, and the ability to exchange accurate information at each hand-off point is crucial to keeping a design on track.  In previous versions of our software, we have given our customers the ability to closely monitor the design and the implementation of their circuits by using Cadence's design constraint technology.  You can learn more about this technology by viewing the Constraint Webinar if you wish. 

With this release of Virtuoso, our users can create hyperlinked schematics and datasheets that can be put together instantly, and enable design review at any moment.  There is no need to fumble around anymore looking for that particular document that is stored somewhere that makes no sense!  Instead, the documentation is stored with the design, and becomes a managed "cellview" just like the schematic or the layout.  Archiving is a snap since all the data you will ever need is now located exactly where it should be -- with the design.  You really can maintain the intent of your custom/analog design whether it is around the room or around the globe.  

New Design Methodologies:  Understanding the "impact" of the analog portion of any design is crucial to the success of on-time arrival for your chip.  In some cases, it is the parasitics and signal integrity of the analog portion that goes awry.  In other cases, it is the integration of the analog into a larger SoC where the problems begin.  In either case, Cadence provides solutions to these problems. 

For troublesome analog, we offer the parasitic-aware design flow, which allows users to determine the impact of design choices much sooner in the design process.  Users can easily include previous knowledge of topologies within the design flow, using these parasitic "estimates" to quickly assess design impact, and then use a combination of constraints and automated layout features to prototype blocks that can be fully extracted and analyzed.  These loops are very short and can provide the designer with a much better sense of the design long before any formal layout is fully committed to paper. 

Once the prototyping is done, the implementation engineer will also have a better direction to take the lead to a faster "ultimate" solution.  They can see the critical design choices and have the tools they are using to implement the design respond to those critical decisions, thus supplementing their own knowledge to create an environment that employs best practices of the manual and automated design flow. If using design constraints, they can be easily checked to see if they were achieved or not, and if not, a notation can be made as to why not.  If the implementation engineers discover that important implementation choices need to be made, they can add information (constraints) and back-annotate these to the schematic to act as the golden reference.

In the case of analog abstraction, the new features for Virtuoso IC6.1.5 include the automatic creation of a Common Power Format file from an analog schematic to test the effects of turning on/off different regions of the chip during its operation.  Through a simple GUI, the analog engineer defines the power needs for his block, and that information along with the schematic generates the proper CPF file.  This file is now used as part of the Cadence Low-Power Solution.  This enables the Cadence Low-Power Solution to extend to the ever increasing number mixed-signal designs.

And lastly, with IC6.1.5 we give you the ability to make your existing methodologies new again with the addition of our next generation Accelerated Parallel Simulator and new waveform technology.  We continue to expand our simulation technology to take advantage of the latest hardware configurations that are available.  We see our customers paying attention not only to their software requirements, but also their capital budgets to make the best choices when it comes to spending for new hardware. 

For customers who invest in multi-core machines, Cadence wants to make sure that you are able to exploit that technology as efficiently as possible.  To that end we are introducing our APS in a "Distributed" mode.  We have been offering our customers speed on single core and multi-core compute platforms. Now we allow you the power to harness multiple, multi-core compute platforms for your most demanding transient simulations to realize peak performance when you need it, particularly at design sign-off time.  And don't worry if those transient files that are produced are tens to hundreds of Gigabytes in size.  Our completely new an upgraded waveform window technology has been tuned with our simulators to provide performance that is unmatched within the EDA industry for large databases.  Combined with its new measurement and extended mixed-signal analysis capabilities, we look forward to you being pleasantly delighted with the new Virtuoso Visualization and Analysis window that comes standard with our Analog Design Environment product line.

In-Design Signoff:  Cadence recognizes the fact that traditional signoff is accomplished today by using expensive tools and the end of an expensive design process to find problems that are now really expensive to fix!  Anyone see a problem with that? ...anyone??  Clearly this is NOT the way to approach daily design.  Instead Cadence allows its signoff technology under the Virtuoso layout user interface to be accessible at any time during the implementation of the design.  For instance, let's say you want to check to see if the IR drop across your power rails was going to be severe enough to miss the power specification.  Or, perhaps the electromigration that is expected in this technology is going to cause a hotspot or a short somewhere in your design.  Or finally, you may be working with sub-45nm technology which you can almost guarantee won't manufacture a proper mask without intervention and compensation during the design phase. 

In the past, a user would leave their layout window, run tools on the outside on the database, and then view the results in a third-party display with the translation and fixing left to user to remember.  That's a completely error prone way to design and has no place anymore in sophisticated design methodologies. An engineer should be able to see critical problem directly on their layout within the context of the tool that they will use to either fix the problem, or verify the problem was fixed using some sort of automation. Now you have a real design flow that creates productivity instead of frustration.  Cadence allows our advanced technology such as Virtuoso Power System, Cadence Litho Electrical Analyzer and Physical Analyzer and our pattern matching DRC technology from the Cadence Physical Verification System all to be used within the cockpit of the Virtuoso Layout Suite.  Find, fix and verify all the time in one location.  You can save your expensive verification tools to simply be a signoff that Cadence was right all along.

Cadence is pleased that our customers, most recently Wolfson, have joined a growing list of public supporters for the expanded Virtuoso custom/analog flow, finding productivity improvements across the board and providing them with a 25-30% time saving for their designs.  For the last 20 years, Cadence has constantly innovated and led the way in solving the complexities of custom/analog design, implementation, and verification.  We look forward to serving your design needs into the future, and sharing a glass of wine as friends when we can.

I encourage you to read the press release, What's New document, other collateral covering the new release of Virtuoso, and discuss your thoughts with me. Are the enhancements what you deem as essential in making you more productive? What do you see out there that you think we should know about?

Steve Lewis

 

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