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Making Friends With Parasitic Effects

Comments(0)Filed under: Parasitic analysis, Custom IC Design, Virtuoso, Virtuoso Analog Design Environment, analog, ADE, ADE-XL, ADE-GXL, Bleasdale, PAD, parasitics

OK, so the title is perhaps a little optimistic but I'm playing off the saying "keep your friends close, but your enemies closer" (The Godfather Part II: Francis Ford Coppola and Mario Puza). The corollary in custom design is to bring the understanding of parasitic effects as early as possible in the design flow, so there is less chance of surprises later.

In custom design there are a few ways to bring your parasitic effects "closer." They are as follows:

1.     The first is perhaps the most painful. It's where parasitic Rs and Cs are manually added directly on the schematic in the hope they are representative enough to cover the layout. So a duplicate of the design is created to protect the original.

2.      Some companies have created scripts that will add a default parasitic capacitance to every net in the design to at least push the design closer to the final result. This can be done during the netlisting phase to avoid editing the schematic.

3.     Other companies have gone a step further and added in a level of structure recognition, so the guesstimated parasitic elements are closer to what a layout would likely produce. The estimates are programmed in, based on prior experience.

4.      Since designs are typically 80% reused, it makes sense to try and leverage the 80% of parasitic information you have from the previous designs. There are a number of ways designers will do this, and depends on how much information is wanted. Again some scripts are often developed to help.

5.     Lastly is the prototype route, where the design is actually constructed very quickly to get access to extracted results. This depends on a high level of automation in the layout generation to make it worthwhile.

Below is a flow that I want to present that covers the last three points and is based on the Parasitic Aware Design (PAD) capabilities of Virtuoso ADE GXL. The six steps are:

1.       Create the parasitic estimates

2.       Explore their effects and make adjustments to the design

3.       Complete the layout and extraction as before

4.       Run the verification simulations

5.       Analyze the pre/post layout impact on performance and recalibrate the estimates from the real extracted results

6.       Reuse the parasitic estimates in subsequent designs as the parasitic estimates are saved as constraints and travel with the design.

PAD Flow

The key challenge to any pre-layout parasitic analysis is getting the estimates in the first place -- and the best estimates are going to be those derived from real data. As I mentioned, some customers have developed the ability to add parasitics based on some heuristics they developed over time and scaled by the rules of the target process. With PAD, these can be included into the flow using the SKILL interface. The advantage is you gain access to all the other capabilities of PAD in ADE XL and GXL for analysis with these effects.

The alternative is to create a prototype of the layout and collect the extracted results directly. With the constraint-driven flow from Virtuoso Schematic Editor XL to Virtuoso Layout Suite XL/GXL, a prototype can be created quickly. Use QRC to extract and you can run verification, then either stitch parasitic networks of interest directly to your pre-layout design or recalibrate any estimated parasitic.

With PAD, you have the most flexibility in incorporating the strategy that makes the most sense to you. With reuse built in, it is now more possible than ever to reduce or even eliminate the iterations back and forth between design and implementation.

What strategy do you use?

Nigel Bleasdale


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