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An Efficient and Fast Verification Flow for Analog Designs Validation using Virtuoso SpectreMDL

Comments(0)Filed under: Virtuoso, RF Design, CDNLive, Spectre, MDL

The emergence of sub-micron technologies has enabled today’s designers to include various digital/analog/RF components in a single chip. The complexity of validating such designs has highlighted the necessity for a robust validation methodology and for an appropriate process for running efficient simulations. At CDNLive! 2008, we introduced will an innovative, efficient and accurate verification flow using Cadence Spectre Measurement Description language (MDL) and explored the strengths and advantages of this flow using IBM environment. This paper exhibited how having such a re-usable, unified and automated simulation environment has significantly improved validation productivity and efficiency, guaranteeing a higher quality of verification for IBM analog designs. Validation of IBM flows and environments using spectreMDL were explored at various levels:

  • Process technologies validation
  • Statistical analog cell characterization
  • Analog circuit analysis specific characterization requiring higher-level control/complexity

Using this flow, capability to execute advanced and complex measurements and run intelligent corner and statistical simulations using Cadence SpectreMDL scripting language was fully demonstrated. Minimal testbench development time while maximizing functional coverage was proven using this methodology by highlighting the portability and re-usability of this flow for several IBM analog designs and characterization of ASIC libraries at 65 and 45nm.

Top Takeaways:

  • Vast Simulation efficiency and speed improvement using spectreMDL for functional verification
  • Capability to perform complex measurements and run advanced analysis without modifying original designs
  • portability and re-usability of spectremdl scripts among various designs and technologies

 

Helene Thibieroz

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