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Analog Design Validation: What is Your Recipe for Success?

Comments(0)Filed under: Custom IC Design, Virtuoso, Virtuoso IC 6.1.3, Virtuoso Analog Design Environment

Every analog circuit design goes through some kind of electrical validation step before release to manufacture. The depth and breadth of this testing depend on the design itself, the end application and of course that all important deadline. When it comes to custom design, there is also an individual factor, as different engineers have different ideas on what validation is required. For example, on one end of the spectrum, you have the Analog Design Grand Master, picking his simulations strategically as if they each cost a drop of his own blood. At the other end, you have the New Designer, who may choose to run a full broadside of tests over a matrix of all conceivable operating conditions. I’ve seen both and both will get the job done, but how do you know you've done sufficient testing?

I might be showing my age here, but back in the day when I was starting out, there was another validation approach where we BUILT the designs on Breadboards to help validate them in the final application. Ah, the good ol’ days.

Anyway, every designer has a validation method, and sometimes they vary so much that efforts are made at a corporate level to set a standard or minimum requirement to create some consistency. Whatever the strategy, here are the core components of an effective electrical validations strategy:

  • Fast setup of testing
  • Reuse of as much testing collateral as possible
  • Run simulations quickly and efficiently, without loss of accuracy
  • Distribute simulations to maximize compute resources
  • Run over environmental, process and operating corners
  • Capture waveforms for analysis and documentation
  • Calculate performance and measure against goals
  • Estimate yield and maximize it
  • Document results for peer review
  • Determine where design adjustments can be made
  • Explore layout effects, even before layout has occurred
  • The ability to script any of the above activities
  • Did I miss anything?

So with so many components, there is a lot of freedom to create your own method, and with that freedom comes the responsibility to not miss anything. If you ask ten engineers on the most effective validation flow, you may get more than ten opinions, since there are many variables and everyone is trying to be the most effective in the time allowed. So as an EDA vendor, it is our responsibility to provide the above capabilities to the users and the flexibility to create innumerable flows to best validate a design. There are many ways to do it wrong, but there are also many ways to do it right and Cadence provides all of the above capabilities within the Virtuoso family of tools, for you can pick what works for you.

OK, so back to the question. What is my recipe for success?

Ingredients:

  • A nominally operating design
  • Virtuoso ADE GXL and Virtuoso Spectre Mega Burst
  •  A sense of humor

Steps:

  1. Start with a fresh design (test for freshness by prodding VDD a few 100 millivolts: The operating region should bounce back to nominal)
  2. Season liberally with test fixtures and SPICE
  3. At this point, you may want to stuff the design with parasitics, to bring out a more reliable flavor (also saves having to cook it twice)
  4. Place on a test plan surrounded by your favorite measurements.
  5. Roast, in an optimization engine over a distributed compute farm, at 350 statistical corners until you reach a golden specification
  6. You can periodically baste the design with constraints to ensure the design is cooked evenly across all goals
  7. Remove from the optimizer when yielding nicely
  8. Serve to your boss with datasheets and a sprig of layout.
Humor aside, I'd like to hear your recipes for successful design validation.

 

Bon appetit

Nigel Bleasdale

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