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# Calculating Large Signal Phase Noise Using Transient Noise Analysis

Comments(1)Filed under: Circuit Design, Custom IC Design, RF Design, MMSIM, Simulators, PLLMy name is Alan Whittaker and I'm in Cadence's Custom IC Proliferation Group.  We support Cadence's Technical Field Organization (the AEs) and Cadence customers during the introduction and adoption of new and advanced EDA technologies.  I'll be posting here from time to time on methodologies and tool features that resolve issues that users have run into during the front-end analog, RF and mixed-signal design process.

I'm first going to address how you can perform a large-signal phase noise analysis on a design block such as a VCO using our transient noise analysis capability in our Spectre circuit simulator.  This approach is in addition to our small signal phase noise analysis which is available using either pnoise or hbnoise analysis in the SpectreRF option to Spectre.

Here are the steps to obtain a phase noise plot from transient noise analysis:

1.  Set up your oscillator testbench circuit for a transient noise analysis (See sourcelink for the Transient Noise appNote - it doesn't discuss the phase noise measurement, but describes how to properly set up the simulation analysis

2.  Add the block freq_meter from the pllMMLib library (\$CDSHOME/tools//dfII/samples/artist/pllMMLib) to the testbench circuit. Important: The instance name for this block must be 'vco_freq'.

If the oscillator output is differential, connect it to the vin_p and vin_n pins on the freq_meter block. If the oscillator output is single ended, connect it to the vin_p pin and connect the vin_n pin to ground. Connect a noConn cell from the basic library to the out_freq pin.

The parameters for this block are (set Tools Filter to veriloga in the CDF parameter form:

• Vthup: Threshold voltage to determine the rise edge of the input waveform. The input waveform period is determined by two adjacent rise edges. Default is 0.

• ttol: The tolerance of the time where the rise edge is determined. Default is 1p.

• outStart: The time-dependent period of the input waveform is output to the file when the time is greater than outStart. Default is 0. To get accurate phase noise measurements, set this to past the time when the oscillator is fully powered up and oscillating at the design frequency.

• outfile: The name of a file to contain time-dependent periods for use in later psd calculations. Specify just the file name, not a path. If outfile is left blank, the default name is periods.txt.

3.  Before starting the simulation, in the ADE window, Select Tools->RF->PLL. In the PLL Macro Model Wizard window, enable PLL Macro Model and select PLL Bench as the Bench Type. Then OK this form.

4.  Run the simulation. The simulation must run successfully to completion in order to get to the phase noise results.

5.  In the Direct Plot form for transient noise there should be a PLL PSD Noise option. This will allow you to plot the phase noise results. If a message appears saying that the PLL Noise PSD data is not available, check steps 3) and 4). If you make any corrections, you will need to re-run the simulation.

The phase noise plot will extend from fmin = 4/tstop to fmax = fosc/2, where tstop is the transient noise simulation stop time and fosc is the oscillation frequency of the circuit.

Important note: You will need to use MMSIM701 and IC5141USR5 or IC613 (or latersubversions) to obtain a phase noise plot from transient noise analysis.