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Custom IC design and design environments

Comments(1)Filed under: Custom IC Design, custom design technology, RF Design, Virtuoso IC 6.1.3

Design environments have come quite a long way from the time I began my engineering career.  It is amazing to see how far we have come from stitching together designs as netlists to run rudimentary simulations, to today’s integrated tools with validation required across a plethora of conditions. In those days, I also remember you only needed one engineer per chip.

 

With today's levels of design complexity, additional tool capabilities are required and yet there are almost as many opinions on the right strategy as there are custom design engineers..... Maybe more!!. However, solutions are starting to coalesce to meet these challenges with one of the biggest challenges coming from capturing the designer intent as additional IP to leverage subsequent reuse/retargeting. 

 

Design strategies and the environments to support today's designs, are not something that happens overnight, but takes time to evolve. With close relationships between EDA vendors and their customers, they mature into tools that can take on the designs of today, while adding the productivity and collaboration required to meet ever tightening deadlines. This is of course, not forgetting the quality goals of the design and the process itself, while allowing for more flexibility and creativity of an ever-increasing design team.

I’m curious about what you think.  How have you seen circuit design and analysis change over the past 5-10-20 years and what do think are the next challenges?

 

Comments(1)

By Daniel Payne on September 30, 2008
I remember SPICE runs that would take over-night and we could do one or two per day. Now with Fast SPICE simulators we have capacity in the 10Million+ transistor range, and runs takes hours to minutes. Of course, we now have to run more corners or even Monte-Carlo to see how our circuits will work across process variations. We can also now simulate HDL along with SPICE level in one simulation environment, instead of throwing waveforms over the wall. The new restricted design rules are deja vu, when I did my first DRAM design for Intel in 1978 they were talking about restricted design rules to improve yields, they wanted to aling all gates in the same orientation. Also at Intel with the first two-level metal process (circa 1982) they wanted all M1 to go vertical and all M2 to go only horizontal, both to improve yield.

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