Cadence Community

Ten Things I've Learned About Formal

tomacadence — Fri, 06 Nov 2009 14:00:00 GMT

2009 is the tenth year that I've spent at least a portion of my time responsible for formal analysis products. As per my profile, my two most recent employers before Cadence were 0-In (now part of Mentor) and Synopsys. Between these jobs I consulted for eight other EDA companies, four of which offered formal products.

You would think that I've learned a few things during the past decade, and I believe that I have. Here are ten lessons I learned along the way, one for each year:

Formal should be applied early – any formal tool that requires an advanced simulation testbench as a starting point can only be run late in the project when there are few bugs left

Formal is about proofs as well as bugs – proving at least some assertions correct instills additional confidence in the design once bugs are no longer being found

Designers should be directly involved in formal analysis – many of the best assertions arise from designers capturing the assumptions in their heads

Automatic assertions can be interesting – while no tool can divine from RTL the intent in the designer's head, customers see real value in many types of automatic checks

You can't neglect the basics – R&D should not focus on exotic features at the expense of language support, robustness, and core engine performance

Assertion-based VIP should be a product, not a freebie – creating quality VIP is hard work that requires a serious resource commitment, so you should get paid for it

Coverage is a good way to link simulation and formal – customers understand coverage in simulation, so anything that formal can do to contribute metrics is a motivation for use

A good marketing story is not enough – licensing a generic formal engine from an external research lab and tacking it onto a “lint” front end does not yield a true solution

Moving users from “lint” to automatic assertions to full formal is not easy – it's better to demonstrate the value of user-specified assertions and formal right up front

It is possible to create a mainstream formal solution – Incisive Formal Verifier (IFV) is a successful product being used by logic designers as well as verification specialists

I learned the first nine things from my direct experience with customers and clients prior to arriving at Cadence three years ago. IFV was already a well established product at that point, so I realized when I joined that Cadence had also learned these important lessons even if some of its competitors had not.

Of course, IFV has continued to evolve since then, and I'm proud to have been a part of its ever-growing success. Now we've introduced Incisive Enterprise Verifier (IEV), offering novel links between simulation and formal analysis. We also have automatic assertions, high-quality assertion VIP products, coverage links, and the methodology and support for wide deployment.

The other day I sat in a Sales review at which I heard that just one Cadence customer, at just one of its sites, is actively using more than 200 IFV and IEV licenses. I could only dream of this sort of deployment in my past involvement with formal. I guess that we’ve all learned a few things in the past ten years!

Tom A.

The truth is out there...sometimes it's in a blog.

"ClubT" Herzelia Israel Verification Seminar Invitation 17 November

teamspecman — Fri, 06 Nov 2009 14:00:00 GMT

Specmaniacs Based In Israel,

Please join us for a day of in-depth presentations and demonstrations of the latest methodologies and technologies for advanced verification this 17 November at the Dan Accadia Hotel in Herzelia.

Specman users and Cadence R&D experts will deliver presentations and demos, as per the following agenda:

08:30-09:00 Registration

09:00-09:15 Welcome and Introduction

09:15-10:30 MDV flow & solutions
--> includes updates to Enterprise Planner, Enterprise Manager, OVM e & OVM Multi-Language, IES-XL siimulation, VIP and the Compliance Management System

10:30-11:00 How to build your own Compliance Management System

11:00-11:15 << Break >>

11:15-12:00 User Presentation: "Choosing verification language and methodology: a first hand testmonial", Wilocity

Technology deep dives:

12:00-12:45 OVM e and OVM Multi-language

12:45-13:45 << Lunch >>

13:45-14:30 Panel discussion: "The Debug Challenge"

14:30-15:45 IES-XL 9.2 technology updates and Specman 9.2 Core deep dives

15:45-16:00 << Break >>

16:00-17:00 Round table discussions with R&D:
- IntelliGen + Gen Debug
- Closure automation
- Verification IP
- Enterprise Manager & Planner
- IES-XL + SimVision
- OVM e / SystemVerilog / Multi-language　

To register, please contact Etty Alon: etty at cadence dot com

Hope to see you there!

Team Specman

Find, Fix And Learn With Cadence Online Support

BobD — Thu, 05 Nov 2009 18:00:00 GMT

We recently rolled out a new online support mechanism that replaces Sourcelink called Cadence Online Support. Point your web browser to sourcelink.cadence.com and you'll notice that it redirects to support.cadence.com.

Improving the search capabilities was one of the major focuses of Cadence Online Support. A single box enables searching across the following areas:

Troubleshooting
Product Manuals
New or Changed Features
Design Info
Blogs and Forums

Additionally, the "Top 3 Overall Matches" across all of these areas are returned. The result, hopefully, is that it's easier to find the information you're looking for. Check it out and let us know how we're doing.

(click to enlarge any of these images)

You can also provide Feedback specifically about any page on the new site. Please take advantage of this capability- we really want to hear what you think and your Feedback will be responded to and tracked to closure:

The new site surfaces up your most recent service requests, and provides a link to create a new service request:

Finally, the site offers a way to learn about how our tools are intended to be used with "Design Topics". Design Topics are the place to look when you don't have a specific bug or issue you're trying to troubleshoot but rather when you want to understand conceptually what Cadence recommends at any given stage on the design process. This information is accessible via Design Topics->View Design Topics on the top of Cadence Online Support pages. Here's an example of the available subtasks within Block Implementation. You can expand any one of these subtasks for more information -or- go directly to any one of the Technical Topics for more information:

So there you have it: Find, Fix and Learn. Click HERE to learn more about Cadence Online Support (login required using your existing Cadence.com password).

Question of the Day: What do you think of the new Cadence Online Suport so far? Leave a comment below or make use of the Feedback mechanism within Cadence Online Support.

Bob Dwyer

DFT Challenge: Evaluating The True Cost Of Test

rgoering — Thu, 05 Nov 2009 14:00:00 GMT

Remember DFT? “Design For Test” faded into the background in recent years as the industry turned its focus to DFM, but if anything test is an even larger concern than it was 10 or 15 years ago. That’s because test is becoming more difficult and expensive at nanometer process nodes, especially with the drive for low-power design and the increasing prevalence of on-chip analog and mixed-signal circuitry.

A recent discussion with Sanjiv Taneja, vice president for Encounter Test at Cadence, showed me that the traditional way we’ve evaluated test costs is way too limited. Test cost is traditionally calculated in terms of capital costs and operating costs. Test engineers focus on optimizing throughput in order to minimize the amount of time each IC spends on the tester. One way that’s done is minimizing test data volume.

While minimizing time on the tester is still important, Sanjiv notes that there are additional criteria that must be considered to evaluate the true cost of test. These include:

Impact of power on yield and test cost. If a test program turns on all the power modes during test, it can result in very high switching activity and excessive IR drop. Good chips can fail on the tester, reducing yield and increasing costs.

Integration of DFT with design implementation flow. Synthesis tools should optimize for testability as well as area, timing and power. Otherwise, test structures can impact routability and timing closure. Poor design/test integration will decrease productivity and thus increase costs.

Analog/mixed-signal test. If analog IP takes up 20 percent of a system-on-chip, it probably accounts for over 50 percent of the test cost. Analog test often requires an expensive, manual approach. Sometimes built-in self test (BIST) is used, but this requires extra work and planning.

Cost of escaped defects. If you think test costs are high, what does it cost for a defective chip to escape detection until system test, or until it’s out in the field? Shipping bad parts to customers can not only kill budgets – it can kill companies.

Ramping to volume production. Process interactions and process variability make it difficult to ramp to volume production at 45 nm and below. Given today’s time-to-market concerns, a delayed yield ramp can be a huge expense.

All of the challenges listed above impact designers, and all can be alleviated through EDA tools. For example, power-aware automatic test pattern generation (ATPG) can make the right tradeoffs between test power reduction and test time reduction. DFT automation tools can hook up BIST engines to a chip test interface, and translate BIST set-up and run-time sequences to test interface ports. Advanced fault modeling and test-point insertion techniques can reduce the risk of escaped defects. And diagnostic EDA tools can speed yield ramps by figuring out the root causes of failures.

Cadence offers such capabilities in the Encounter Test product line, which is being shown at this week’s International Test Conference (ITC) in Austin, Texas. The ITC program, meanwhile, has a strong DFT emphasis. It includes a keynote and a plenary invited address that focus on the integration of design and test, as well as panel discussions on DFT for analog and low-power design. Cadence has representatives on both panels.

DFT has been around for a long time. I started writing about it in 1984 for Computer Design magazine, well before the term “EDA” was even invented. Here we are now, 25 years later, and it turns out that DFT is more important than ever. Some things never go out of style.

Richard Goering

Things You Didn't Know About Virtuoso: ViVA (Part 2)

stacyw — Wed, 04 Nov 2009 14:00:00 GMT

This week's installment, boys and girls, is brought to you by the letters H, V, m & a and by the symbol %. Apologies to anyone out there who didn't grow up with Big Bird and Cookie Monster. (Is that even possible?)

Remember those letters, we'll get back to them in a bit...

First a couple of FAQ's about axes in ViVA.

How can I tell which axis a signal is associated to?

Well, this isn't the easiest thing in the world, but if you look very closely, you'll notice one or more colored bars next to each axis title. They only appear if you actually have more than one axis on your graph, which will happen if you plot quantities of different units (like voltage and current). If you look closely, you'll see that the colored bars on each axis correspond to the colors of the plotted signals associated with that axis.

How can I move a signal from one axis to another (or to a new axis)?

This is easy. Simply select the signal you want to move by clicking on the waveform or it's name in the legend (don't forget you can use the Alt key--one of the sponsors of last week's episode--to quickly see which signal is which). Then, from the menu, select Trace->Assign To Axis and either select the axis you want to move it to or choose New Axis to do just that.

Now a word from our sponsors...

The letters H, V, m & a are the bindkeys you use to create interactive marker measurements in ViVA.

H (that's capital H, or Shift-H) will place a horizontal marker and Shift-V will--no fair, you peeked--place a vertical marker.
m (that's little m, without the Shift) will place a single point marker.
a (again, lowercase) will create a delta marker between itself and the most recent "m" marker.

There are several nice things about these markers.

You can have as many of them on your graph as you like.

You can select Marker->Show Table to get a tabular readout of all your marker intercepts with your signals. There's also an icon to do this. I'll let you find that on your own. If you move the markers (or rerun the simulation), simply press the Update icon in the marker table to refresh the values. This table can then be saved to a file for documentation.

They stay where you put them (unless, of course, you drag them to move them somewhere else--or delete them)

Speaking of dragging, you can drag the marker labels around to position them wherever looks nicest, without disconnecting the marker from the trace.

Speaking of marker labels, that's where our final sponsor comes in, the mysterious % symbol. First, double-click on the marker label to bring up the marker attributes form. The marker labels can be customized and the % sign is used to create some powerful types of formatting. The complete list can be found in the Virtuoso Visualization & Analysis Tool User Guide, but here are a few useful examples:
- %X, %Y will display the X and Y coordinates (%x, %y will display the 2nd X and Y coordinates for delta markers)
- %W, %H will display delta X and delta Y
- %N will print the name of the trace (handy on a crowded graph)
- My personal favorite, %E, works with the Expression field in the form to allow you to pull an expression from the calculator buffer or one of the calculator memories (more on that in a future episode) and annotate it directly onto the graph. This way you can get a clear visual representation of what is being measured. (Note: This was broken for a while, so make sure you've got the latest IC6.1.3 ISR if it doesn't work for you)

Now you can use the File->Save As Image or File->Print menu to save your beautiful graph to display at your design review.

Stacy Whiteman

OVM Innovation Means Business

Adam Sherilog — Tue, 03 Nov 2009 20:01:00 GMT

Today, Cadence recognized it's OVM team for their innovative contribution to the Cadence enterprise starting in 2008. Why enterprise? To me, enterprise is the most exciting part because it underscore how the OVM has rallied all of Cadence verification around a common cause which has both polished our image as the verification leader and created new business opportunities.

To understand the impact, we need to step back to 2007. SystemVerilog implementations were just coming together and VMM was a mix of SystemVerilog and Vera. e and eRM, on the other hand, were well established with years of success at this point. So why OVM? To unify the ecosystem. OVM was the first open, multi-vendor, scalable methodology architected for multi-language. Looking back, this statement seemed simple enough, but the simplicity is the innovation.

Open. It doesn't get more simple than that, but it was a rallying point in the marketing and development that changed everything. The OVM started as both Apache licensed and multi-vendor and, in fact, remains the only verification methodology embodying both. With a community now 8000+ strong as measured on the OVM World website, the marketing and development simplicity certainly resonated.

Scalable. The OVM introduced to the SystemVerilog community the agent-architecture used by the e community for years. The concept itself is simple -- a consistent way to describe verification components for reuse -- but is backed by a sophisticated implementation. The innovation here is all technical -- place the burden of complexity on the methodology/library developer and provide the consumer with ease of use.

Creative: Building on past success was important, but new solutions were needed to win the hearts and minds of the nascent SystemVerilog community. The development team built an advanced factory mechanism, field automation, test classes and test selection mechanism, and more many of which have found their way into competing libraries due to that bold move to be open. As the next point will show, the team has never looked back. The creative stream is still flowing with callbacks, configuration mechanism, OVM multi-language capabilities, and much more.

Passionate. Did that one surprise you? If you have talked to anyone from the extended OVM team -- and there are hundreds of us -- that is our simple connection. I've been with Cadence for 18+ years and working with the OVM rekindled the start-up in us. We argued. We fought. We united and we delivered. And we are still doing that today. The simplicity of that emotive drive assures that you get the best out of us all the time, every time. Maybe that was latent in the team for a while, but we are certainly bringing it now. And for those on the internal team, you know we were doing that even today. :-)

I know this blog was a "pat on the back" for the OVM team, but we all need to step back from time to time and assess ourselves. We're proud of the innovation we have brought to verification and even more proud to say we ain't done yet!

=Adam Sherilog on behalf of the whole OVM team

Today's Innovation Awards and The "Trailblazer" Marathon

jvh3 — Tue, 03 Nov 2009 19:00:00 GMT

Today myself and the whole Trailblazer team are proud to celebrate the success of my colleagues' winning awards on Cadence's "Innovation Day". In specific reference to the verification segment winners, over the past year I've had a front row seat to their struggles. They will be too modest to admit this, but let me tell you there were times when it was really dark for them.

Boston Marathon: Hearbreak Hill

But despite temptations to settle for less ambitious solutions, guided by their years of industry experience, deep technical expertise, collegial teamwork, as well as the strength derived from their hobbies (like running marathons -- no kidding, see above), they persevered to deliver on their innovative roadmap.

Fast forward to the present:

The Trailblazers are currently in mile 20 of a product development marathon to automate verification in ways no one has dared attempt before. In Boston Marathon terms, it feels like we are ascending Heartbreak Hill; so to say the least it's encouraging to have our award-winning colleagues cheer us forward as we count down the remaining miles!

Joe Hupcey III

P.S. Fellow blogger and Cadence Innovation Day award winner Adam Sherer is a real live marathon runner, who has requalified and committed to running his 8th consecutive Boston Marathon for the benefit of Children's Hospital. Beating the Patriot's Day rush by sponsoring Adam now will no doubt inspire him during his 5AM winter training sessions!

Cadence and Very Cool Stuff

Rich Owen — Tue, 03 Nov 2009 17:44:00 GMT

One of the very cool things about my job is that I get to see all kinds of new stuff early. I’m privileged to be involved in technology roll outs, and so get to be involved in early discussions with R&D, Product Engineering, and Marketing. And, I gotta tell you, there is very cool stuff coming out.

As I think we’ve established, I’m a geek. (And there’s my daughter again, rolling her eyes, and saying, “tell’em something they don’t already know, Dad.”) And so when I get a chance to see some of the new stuff being prepped by our R&D teams, I get pretty excited.

Here’s just one thing that’s on the burner – a method to explore the power solution space. I met a good customer today, and he very accurately pointed out that Power Shut Off (PSO) is a system function. The system designers very clearly know what blocks can be shut off when – it is a system function. But Multi-Supply Voltage (MSV) is another matter. Fundamentally MSV is about trading off speed for power – the faster you need it, the more power you’ll need. And this really means that any effective power estimation solution needs to consider the libraries, architecture, and expected implementation. If you don’t consider these, you’re not looking at the full picture. In the absence of the ability to estimate the impacts of timing, any kind of architectural analysis is largely meaningless. I mean, why not set the voltage on everything to 0.1v? You’ll save a ton of power. Of course timing closure might be a bit challenging.

So we’re getting ready to come out with something that will allow exploration of the power solution space; something that will really allow you to trade off speed for power. You set up the starting points – stuff like the libraries, constraints, and the like. You then set up the bounding conditions – the allowed solution space. The tool will then go off and run through the scenarios, identifying the best combination of voltages that will meet your timing and power targets. Under the hood, the tool is taking advantage of RTL Compiler’s target setting function to identify whether a given scenario will meet the requirements.

This will take the guess work out of MSV designs. What I really like is that this is the same technology that will then produce a production quality netlist. So correlation is not an issue – there’s no magic library conversions or RTL manipulations to produce this. You pour RTL, libraries, and constraints in, and you get the right scenario out. And you can then just push the button to implement the scenario.

As I mentioned, I was at a customer today. With me were two members of the R&D team – both PhDs and both widely known in the industry. We were presenting the challenges of low power design and how Cadence flows and methodologies solve those challenges. Now these are seriously smart people, and to see their passion and enthusiasm for the technology was contagious. These R&D guys really know their stuff, and they’re committed to making my customer successful. Cadence has (obviously) being going through a down cycle. But with guys like these, and with the technology we’ve got, no one should count us out. Nor should anyone discount our commitment to our customer’s success. We still have the best flows and tools and technology, and we’re still driving the innovation in the industry. We’ve not changed our passion or commitment one little bit – and don’t let anyone tell you differently.

Oh, and here’s a chance for you to hear about the latest innovations in the Front End Design space: Cadence is hosting the annual FED Event in San Jose on Nov 10. This is an event with R&D leaders discussing the new technology and innovations coming out in the next releases. You’ll hear from all of the R&D leaders in this space, and hear from other customers using our technology. And you’ll even get to see me – I’m on a panel offering my perspective about FED. Sign up at www.secure-register.net/cadence/ld_event2009 and I hope to see you there.

Rich Owen

Greatest Moments In EDA Innovation

rgoering — Tue, 03 Nov 2009 14:00:00 GMT

Innovation is the lifeblood of the EDA industry, and it is only because of innovation from many sources – including academia and industry – that modern IC design is possible at all. Today at Cadence (Nov. 3, 2009), we are celebrating Cadence Innovation Day. As such, it seems like a good time to consider the “greatest” innovations that shaped our industry.

Also this week, the EDA Consortium will present the 16th annual Phil Kaufman award to Prof. Randal Bryant, whom I interviewed for a recent Industry Insights blog. This award is the EDA industry’s highest honor, and a look at the past 16 award winners provides some good background into the history of EDA innovation.

Here are my nominations (not necessarily in order) for the “greatest moments in EDA innovation.” Any further suggestions are welcome.

1. Spice simulation

Spice (Simulation Program with Integrated Circuit Emphasis) was one of the very first EDA programs, and it’s still the gold standard today for analog and custom circuit simulation. Spice was derived from a program called Cancer, which came out of a class project led by Prof. Ron Rohrer (2002 Kaufman award winner). Prof. Donald Peterson (1995 Kaufman award winner) oversaw the Cancer rewrite that became Spice, which was first publicly presented in 1973.

2. Verilog HDL

The Verilog language ushered in the present era of language-based IC design, and made RTL synthesis and simulation possible. Verilog was developed by Phil Moorby, 2005 Kaufman award winner, at Gateway Design Automation in the early 1980s. When former Cadence CEO Joe Costello won the Kaufman award in 2004, one reason cited was Cadence’s 1989 purchase of Gateway and subsequent opening of Verilog for standardization.

3. Multi-level logic synthesis

Nearly all complex digital circuits are designed with logic synthesis today. Synthesis was first applied to two-level logic with programs such as Espresso. However, a breakthrough in multi-level synthesis was required to make the technology practical for contemporary IC design. That came about in the 1980s through efforts such as IBM’s Yorktown Silicon Compiler project and the MIS and SIS programs from U.C. Berkeley. Prof. Robert Brayton, 2007 Kaufman award winner, and Prof. Alberto Sangiovanni-Vincentelli, 2001 Kaufman award winner and Cadence board member, collaborated in the development of Espresso, MIS and SIS.

4. Automated IC layout

Today’s ICs could not be designed without placement and routing software. Prof. Ernest Kuh, who was at U.C. Berkeley from 1956 to 1993, helped lay the groundwork for IC physical design in the 1970s and 1980s. He won the 1998 Phil Kaufman award for his foundational work in circuit layout theory, partitioning, floorplanning, placement and routing.

5. Structured VLSI design

EDA innovation is not just about tools and algorithms – it’s about methodologies. Prof. Carver Mead, winner of the 1996 Phil Kaufman award, is known not only for his work in areas such as silicon compilation, but also as the co-author along with Lynn Conway of “Introduction to VLSI Design” in 1980. This seminal book set forth a structured methodology for the design of large-scale ICs.

The innovators mentioned above have set a high bar to follow. But given the emphasis that Cadence is placing on innovation and R&D, it just could be that someone at today’s innovation awards ceremony will follow in their footsteps.

Richard Goering

What's Good About Innovation at Cadence? – It’s Alive and Well and Increasing!

Jerry GenPart — Tue, 03 Nov 2009 14:00:00 GMT

I'm switching gears this week from my regular SPB technical product posts to focus on an annual Cadence event - Cadence Innovation Day.

Today Cadence will honor the 2008 recipients of the Excellence in Innovation Awards. This year, 35 winners will be celebrated amongst their peers from all geographies and organizations - 13 of this year's recipients are from locations outside San Jose.

Adam Sherer is one of this year's recipients and a fellow blogger - so send him
congratulations on his Blog.

Cadence has been a consistent leader in innovation since its foundation 21 years ago. One measure of innovation is the number of patents issued. With more than 800 U.S. patents issued (an additional 150 international), Cadence holds far more patents than any other EDA company in the world.

"The Excellence in Innovation Awards program recognizes our best inventors and most significant inventions," said Interim Chief Technology Officer Charlie Huang, "These annual awards are a reminder of just how innovative Cadence is. We want to recognize our company's great spirit and tradition of innovation with a day of celebration and appreciation."

"The Excellence in Innovation Awards program was established to encourage, promote, and recognize the wealth of innovative, internally developed technology," said Mike Williams, Vice President and Associate General Counsel, and program manager.

Our customers rely on Cadence for innovation leadership. "Leadership in innovation is fundamental for customers to choose Cadence as their trusted design partner," said Tom Cooley, Sr. Vice President, Worldwide Field Operations. "Innovation is and must always be part of the Cadence brand."

Bringing innovation a bit closer to my own organization - the Global Field & Customer Support (GFCS) team - we've initiated a web based idea submission and management approval system (called iInnovate) for GFCS employees late last year. This Wiki based site contains all the details for everyone to review and measure - submissions, ideas approved and implemented/referred, awards presented, process info, etc. It's a very easy and comprehensive innovation enabler!

The goal that Dan Rourke, VP Customer Support established was to cultivate a sustainable innovation engine among all GFCS employees to empower us to submit ideas and increase the value-add we provide to both our external and internal customers. A team within GFCS was formed to look at innovation best-practices among companies and deliver a web-based approach to streamline all aspects of delivering innovation across the GFCS team. There are several categories available on the web site to help focus innovators in key areas - among them being Customer, Process, and Technology. Everyone in GFCS can view ideas submitted, check on the status of the ideas, and see how the iInnovate review team and GFCS management has dispositioned each submission. There are inspirational quotes updated periodically, and the GFCS management team updates the site with new directions they'd like to see employees focus for a period of time (usually 3-6 months). This allows everyone to think within the current strategic focus and provide new ideas to support these efforts. More than 40 new ideas have been submitted through the iInnovate site since we began with more than 15 ideas implemented or referred to other teams for implementation.

Some of the GFCS's ideas that have been implemented are:

Enhanced videos/screen casts on Cadence Online Support
Cadence Online Support product release schedule updated
Added an “All Products” choice in the Cadence Online Support search selection

It's great to work for Cadence where innovation is recognized at the corporate level and employees are energized within my own group to continue to explore new innovative methods to improve how we work with our customers.

As always, I welcome your suggestions and discussion on this topic.

Jerry "GenPart" Grzenia

Innovation != Invention

Bob Loblaw — Tue, 03 Nov 2009 14:00:00 GMT

There's a common misperception, especially in technology fields, that invention and innovation are interchangeable terms. Innovation is a new solution to a problem, a new way of doing things, something that creates new markets and categories. Yes, an invention can enable innovation, but it is not a prerequisite. Take the iPod as an example. When it came out in 2001, there were already plenty of MP3 players available. Most were flash-based, when flash memory was still very expensive. The mainstream...(read more)

Things You Wish You'd Thought Of...But You're Glad Someone Did!

stacyw — Tue, 03 Nov 2009 14:00:00 GMT

On Tuesday this week we are celebrating "Innovation Day" here at Cadence, honoring inventive engineers across the company.

I must admit that most of the time I get so bogged down with the latest customer questions or figuring out how to help people learn about the latest features that I forget about all those folks in R&D whose raison d'etre is to come up with new and better ways of doing things. And there are plenty of them. Sometimes their efforts aren't really obvious to the end user (a new algorithm under the hood, or new ways of helping us develop and support the software), but they still make a big difference.

Innovation doesn't have to flashy. Maybe it's a small idea which could make a big impact. Maybe it turns out to be just too big. Maybe it's finding a new way to make people change their old behaviors.

Whatever the size or scope of the ideas, we need innovative thinkers at all levels in the world today to solve problems and make our lives better. I'm very glad Cadence has chosen to set aside a day to recognize our own very talented engineers.

Stacy Whtieman

Emulation Is Here To Stay

Ran Avinun — Tue, 03 Nov 2009 00:29:00 GMT

A recent blog by Brian Bailey covered the emulation war. I would like to correct some of the facts Brian has mentioned and also add my own comments. First, Brian, you owe Cadence an apology :) You forgot some of the emulation announcements from Cadence. You mentioned Nethra Imaging, AMD and Silicon Hive as the ones that were announced in the past year. You forgot the following announcements: Sharp , Netronome , ICT and the recent nVidia announcement about their Palladium usage at the Fermi project...(read more)

From Cadence Earning Call This Week

Ran Avinun — Mon, 02 Nov 2009 19:01:00 GMT

In system development, we have focused on two key customer challenges. First, we are increasing their productivity by elevating design and verification to the next level of abstraction. This quarter, we announced the industry’s first transaction-level modeling, or TLM, design and verification flow. We also announced integration of this flow to support leading embedded software environments, enabling OVM -based, hardware / software co-verification. Second, we introduced a system validation solution...(read more)

Improve Productivity Through Communication and Learning

jasona — Mon, 02 Nov 2009 15:00:00 GMT

I regularly spend time talking to people about the importance of the connection between embedded software and hardware design and verification. If you have been following my writing on cadence.com you know that it takes more than tools to succeed on a project that depends on hardware and software working together. I have written about embedded software verification and how to improve it. I have also written about companies that have reorganized people to report to common management that is responsible...(read more)

Users Outline New Approaches To Mixed-Signal Verification

rgoering — Mon, 02 Nov 2009 14:00:00 GMT

At the Cadence Mixed-Signal Design Summit, held Oct. 27, I had a hard time finding a seat in a packed auditorium. One reason for the summit’s popularity was its hands-on, practical nature. A series of user presentations showed how designers are solving real problems in mixed-signal verification. Below are quick summaries of five such presentations.

Jess Chan (Qualcomm), Robert Milkovits (Jazz), Prasanth Aprameyan (Micron), Kumar Abhishek (Freescale),
and Yuval Shay (STMicroelecrtronics) presented at the Mixed-Signal Design Summit (left to right).

Top-down approach guides mixed-signal simulation

Yuval Shay, staff engineer for mixed-signal verification at STMicroelectronics, gave a presentation entitled “Mixed-language simulation of sigma-delta ADC with AMS Designer.” In the presentation, he outlined a “top-down” hierarchical verification methodology that uses the Cadence Virtuoso AMS Designer simulator within the Virtuoso Analog Design Environment (ADE).

The idea behind the top-down methodology is to start verification as soon as the design effort starts. To accomplish this, engineers create models at the highest level possible and slowly expand the hierarchy “downwards,” substituting behavioral models with transistor-level models until full-chip, transistor-level simulations can be executed. The same testbench developed for the behavioral level can run the full transistor-level design.

Shay identified three basic steps to ST’s methodology:

Partition design into analog and digital domains. Simulate analog blocks with Virtuoso Spectre simulator (Spice) and digital blocks with Cadence NC-Sim.
Run signal path verification for modulator and digital filter.
Run full-chip functional verification, including transistor level models and post-layout netlists.

Shay said this approach has “proven to be a very good solution” for his company’s needs.

Modeling methodology moves real numbers

Simulating real number traffic is an important part of mixed-signal simulation, but there are some tricks to it, according to Jess Chen, senior staff engineer at Qualcomm. His presentation was entitled “A modeling methodology for verifying functionality of a wireless chip.”

There are some challenges with real number traffic in event-driven simulations, Chen said. He prefers a “baseband equivalent” approach that passes multiple real numbers on a single wire. Advantages: the models run fast by suppressing the carrier, they produce realistic signals at the DAC outputs and ADC inputs, IQ swapping is easy to detect, and noise is easy to include.

Chen said his group considered various options for simulating real number traffic, and used a PLI function. This makes it possible to pass real vectors between Verilog modules, use bidirectional real number traffic, switch between voltage and current on the fly, and use a resolution function for real number drivers. Qualcomm applied this methodology to a wireless SoC and found over 100 functional bugs before tapeout.

Full chip Spice simulation really does work

Think full-chip Spice simulation is impractical? Kumar Abhishek, senior analog and mixed-signal design engineer at Freescale Semiconductor, showed how it can work in a presentation entitled “Full chip Spice simulation methodology for zero defect silicon.”

What Abhishek described is actually a Verilog-AMS/Spice co-simulation approach. In a microcontroller SoC, he used Spice models for blocks such as ADC, DAC, voltage regulator, LCD controller, and clock generator. Verilog-AMS models were used for a crystal driver, analog sensor model, and supply driver. Verilog-AMS monitors were used for display, clock profile, data converter, and power monitor.

Abhishek showed a list of microcontroller verification challenges, including those related to analog behavior, power management, and pad rings. He said the AMS/Spice co-simulation approach is “robust” or gives 90 percent confidence in most cases. He also showed a number of test cases and talked about setup times and simulation run times. For example, in a test case with 6M transistors, power-up simulations took a setup time of 2-3 days and a run time of 15 hours.

He concluded that the proposed full-chip Spice methodology is useful for catching corner cases for complex mixed-signal SoCs, especially in complex power-gating scenarios. Abhishek noted, however, that it is “not a replacement” for the existing SoC mixed-signal verification flow, but a complement that can help attain 100 percent coverage for complex protocols.

How to capture design intent

Robert Milkovits, director of technical support at Jazz Semiconductor, gave a presentation entitled “Capturing AMS design intent.” He first spoke of “design intent holes and misses,” including:

Incomplete coverage for circuit analysis
Design sensitivity not uncovered
Parasitic effects on performance
Layout implementation discrepancies
Insufficient time for optimization and coverage analysis

Milkovits talked about how Cadence Virtuoso platform updates in IC6.1 help users represent design intent. He noted that constraint management is integral to design intent, and showed how Virtuoso constraints help “address both the big picture and the design details.”

A look at flash memory verification

Prashanth Aprameyan, senior verification manager at Micron Technology, spoke on “Mixed signal verification – a NAND memory perspective.” He said that NAND memory verification is very similar to other mixed-signal verification, and noted that “for us, verification cost is as important as design cost.”

NAND flash memory includes a memory array, sense amplifiers, high-voltage circuits, controller and logic, and low-voltage analog, pad and I/O. Micron uses both Verilog-A and digital Verilog modeling of the memory array. The Cadence Virtuoso UltraSim simulator, a fast Spice simulator, is extensively used for NAND flash verification. Micron is also investigating wreal behavioral modeling with Verilog-AMS.

Apremeyan noted that full-chip simulation time is becoming prohibitive, that it would be nice to have all electrical aspects of verification under a single tool, and that design for yield (DFY) analysis in fast Spice would be helpful.

Q&A panel

In a Q&A panel following the presentations, panelists fielded questions on the difficulty and cost of developing analog behavioral models, whether designers should do their own verification, modeling for performance verification, SoC-level and IP challenges, and test.

The summit also featured a keynote by Paul Emerson, general manager for the analog and logic business at Texas Instruments, and several presentations on Cadence’s mixed-signal solutions. Videos will be available on-line in November. Another review of the summit can be found in Paul McLellan’s blog.

Richard Goering

OVM Tricks and Treats

Team genIES — Fri, 30 Oct 2009 20:30:00 GMT

Your kids may be going house to house for treats, but you can get a big OVM sugar rush from Cadence's OVM World contributions. Each delectible nugget is wrapped in documentation that helps you savor all the goodness. So reach into the bowl and indulge in these methodology sweets!

Callback Mechanism

From day 1 the OVM has employed a factory mechanism for both simple reuse and multi-language consistancy. While factories are the generally accepted practice for object oriented languages, users migrating to the OVM from other methodologies may be more comfortable with extending procedural and structural elements using callbacks. This donation adds callbacks to the OVM SV (SystemVerilog) library.

Compliance Checklist

With it's roots in eRM, users of the OVM can access to the collective experience of 5000+ tapeouts over nearly a decade using the contributed OVC (OVM Verification Component) Compliance Checklist. Since each donation is open, it is easy for the ecosystem to take them and create value-added products. Amiq has done this by automating the checklist in an OVM DVE. A demo of the OVM e version was recently blogged and one demoing the OVM SV (SystemVerilog) version will be up shortly.

Objection Mechanism

When everything works perfectly, life is just so easy. Unfortunately (or fortunately for those of us who need the work!!), it rarely works that way. The Objection Mechanism package adds a number of capabilities to help coordinate and manage complex testbenches. It includes hierarchical status coordination, objection handling, simplified end-of-test coordination, heartbeat detection of malfunctioning objects, and more.

Fourth in alphabetical order, this most downloaded contribution on the entire OVM World website with 1500+ at the time this blog was written. In its second release now, this register package contains significant improvements recommended by our customers and the OVM Advisory Group (OAG). Among these include greatly improved capacity/performance, multi-bus system-level control, alignment with IP_XACT 1.5, and much more. We do recommend upgrading from our 1.1 version and there is documentation on how to do so. The most-often asked question is "when will there be a joint package" and we are continuing to work with Mentor on that so say stuned to the OVM World and this blog!

Regression Speed-Up

OVM messages are critical to understanding both nominal and error conditions in your testbench. However, when you scale up the environment those innocent string manipulations can become very expensive regardless of the verbosity settings. This contribution show you how to optimize your messaging to improve OVM testbench performance. Like all of our contributions, this should improve your life regardless of the simulator you choose. Of course, this blogger would prefer y'all use Incisive Enterprise Simulator!!

Christmas / Hanukkah / Kwanzaa is coming next. Will there be more treats?

Yes! The genIES are hard at work conjuring up more magical treats for you so visit the OVM World contributions area and this blog frequently or sign-up for the RSS feed.

=Team genIES

Why Verification Engineers Are Like Football Players

Adam Sherilog — Fri, 30 Oct 2009 19:01:00 GMT

Is it their raw power? Is it the cheerleaders? Why are verification engineers like football players? It's because they know how to squeeze the maximum performance out of their resources to win the verification game. Charlie Dawson, Senior Engineering Manager at Cadence, has been leading teams that build performance into our products for years and has taken some time to put the whole game in perspective. Read more about it in his article published in EDA Design Line.

The article follows a similar thought to the paper Charlie delivered at CDNLive! San Jose last month. That paper should be post shortly with the rest of the CDNLive! content.

If you have any questions or want to follow-up on any of the points in the article, feel free to post you comment here or send them to genIES@cadence.com.

=Adam Sheriperf (just extending the "Sherilog" brand to verification performance. :-) )

Encounter How-To: Write Text to The Log File With "Puts"

BobD — Fri, 30 Oct 2009 16:00:00 GMT

Here's a simple but useful tip that shows how to write to the log file using the Encounter command "Puts"...

In TCL, the "puts" command is use to write information to the console -or- to a file. For example:

encounter 63> puts "hi"
hi

-or-

encounter 64> set outfile [open test "w"]
file18
encounter 65> puts $outfile "hi"
encounter 66> close $outfile
encounter 67> more test
hi

But, how do you write information to the log file? Although it's possible to get the name of the current log file (and that's a useful tip in itself):

encounter 68> getLogFileName
encounter.log207

...it's not clear how to get the handle of the log file so that we can write to it with puts. It turns out- you don't need to because there's a special built-in command called "Puts" (note the capital "P") that writes to the screen -and- to the log file:

encounter 69> Puts "hi"
hi

Note: that the string is still written to the console.

Note: too that the string is written to the log file:

encounter 70> tail -1 encounter.log207
hi

Writing to the log file can be particularly useful when troubleshooting a script and you want to write checkpoint statements that you can later search for using a text editor.

I hope this is useful.

Bob Dwyer

What's Good About Net Color Override in Allegro? Check Out The SPB16.2 Release and See!

Jerry GenPart — Thu, 29 Oct 2009 16:00:00 GMT

Color assignment in Allegro PCB Editor has been accomplished with either a class/subclass color assignment or a color assignment done with the highlight command. With designs becoming more complex, it's desirable to be able to assign colors, including custom colors to independent objects.

Database elements may be displayed using either the class/subclass color or a single color assigned to an element, also known as a custom color. To assign a custom color to an entire net or to its pins, vias, clines, shapes, or rats, you use the Nets grid. Assigning a custom color automatically enables the custom color state for that element as well, meaning that the custom color displays in the design canvas.

You can also define how the custom color displays the element using a combination of states — none, highlight or custom color state, or highlight plus custom color state — all of which may be set independently. Highlighting or custom colors are set or unset by right clicking and choosing Set Highlight State or Clear Highlight State, respectively in the color chip. If an object is highlighted the text for that object type will be in bold.

To prevent a custom color from displaying in both the Nets tree and the design, right click and choose Clear Custom Color. A color box without a color assigned to it has no custom color state. These custom color and highlighting states affect the display of the element as follows:

Custom Color	Highlight State	Custom Color State	Display Using
Yes	No	No	Class/subclass color
Yes	Yes	No	Highlighted color
Yes	Yes	Yes	Highlighted color
Yes	Yes	No	Custom color. No highlighting
No	Yes	No	Highlight with temporary highlight color
No	No	Yes	Custom color with tempororary highlight color
No	No	No	Class/subclass color

As always - I welcome your question & suggestions.
Jerry "GenPart" Grzenia

User Interview: How To Estimate Power Early

rgoering — Thu, 29 Oct 2009 13:00:00 GMT

Early power estimation makes it much easier to manage IC power, according to Camille Kokozaki, director of design automation services at Integrated Device Technology (IDT). At the recent CDNLive! Silicon Valley, he presented a case study of architectural power estimation with a 65nm system-on-chip with 250K logic cells and a maximum frequency of 400 MHz.

Kokozaki described a flow that uses five steps:

“Back of envelope” estimations in spreadsheet provide assumptions about voltage, dynamic power factor, leakage power factor, design for test overhead, and other factors.
Power estimation from InCyte Chip Estimator uses a provided model library. InCyte estimates dynamic power sensitivity versus activity.
Cadence Encounter RTL Compiler provides estimation from early synthesis run.
More accurate estimation based on full synthesis netlist.
Power calculation from post-layout netlist.

Accuracy increases with each successive step, but the higher levels of abstraction provide a greater ability to influence power.

In an interview following his presentation, Kokozaki discussed his approach to power estimation further. In the attached video clip, he discusses the importance of power analysis at an architectural level, and talks about his use of spreadsheets, InCyte, and pre-synthesis and post-synthesis power estimations.

If video fails to launch click here.

For the chip described in the CDNLive! case study, IDT employed clock gating. Kokozaki said IDT also uses more advanced power management techniques where appropriate.

Kokozaki had a warning about the use of activity levels in power estimates. “Be very careful about activity and what it means,” he said. “There are cases where a 10 percent activity for a particular mode can consume even more power than a 15 percent activity rate on a different mode in the same design. You have to know what you’re putting in there. I also advise people to not go overboard and use a much higher activity rate than what they end up seeing.”

Richard Goering

4 Minute Demo: OVM e Compliance Checks Added to AMIQ's DVT

teamspecman — Wed, 28 Oct 2009 15:00:00 GMT

Specmaniacs rejoice: long time Verification Alliance partner AMIQ has just added OVM e compliance checking to their "DVT" integrated development environment (IDE). Here is a 4 minute video demo with the highlights of this new capability:

If the fails to launch click here.

To get the full scope of the DVT tool and AMIQ as a company, recall the 5 minute general demo of the tool in an earlier post, and this interview with AMIQ's leadership. Alternatively, you can cut to the chase and email etools@amiq.ro to ask AMIQ for an evaluation license. There is additional information at www.dvteclipse.com, including the complete set of DVT manuals.

Happy coding!
Team Specman

P.S. Do you have an e language or Specman-related product, utility, plug-in, or shareware that you would like to promote? If so, please contact Team Specman offline and we’ll work with you to introduce and discuss it via this blog.

Panelists: 32 nm HKMG Is Ready To Roll

rgoering — Wed, 28 Oct 2009 14:30:00 GMT

The 32/28 nm Common Platform high-k metal gate (HKMG) technology is “ready and open for business,” according to the title of a breakfast panel at the ARM Techcon3 conference Oct. 22. Panelists from IBM, ARM and Cadence talked about the benefits of HKMG, the requirements it places on the design flow, and the deep and early collaboration that made a supporting ecosystem with libraries and tools possible.

All of the panelists talked about the Common Platform/ARM/Cadence collaboration, which began in 2008 just a few months after the Common Platform started its process development work. Starting that early is very unusual, according to Jaya Jagannathan, director of semiconductor technology business development and marketing for IBM’s System and Technology group.

Jaya Jagannathan (IBM), Rob Aitken (ARM), and Vassilios Gerousis (Cadence)
discuss the Common Platform 32 nm HKMG technology (left to right).

HKMG, introduced by the Common Platform at 32 nm, promises significant power and performance advantages. The main benefit of HKMG, according to Jagannathan, is that it allows the scaling of gate lengths to continue. This had almost stopped at 90 nm, he said, because gate oxides were only a few angstroms – and atoms – in width. But HKMG, which uses thicker materials, allows scaling to resume. Further, he said, HKMG allows the “densest SRAM in the industry at 32 nm.”

Jagannathan also said that the 32/28 nm process uses a “gate first” approach in which gates are processed towards the beginning of the process flow. This, he said, allows a 50 percent scaling from one generation to another, while minimizing design restrictions and avoiding the addition of complex process steps. “Based on all the work we’ve done jointly, I can tell you that we can achieve the gate density we promised, we can achieve the performance we promised, and we can achieve the simplicity that we promised with gate first,” he said.

Why 32/28 nm? 32 nm is the main process node, but it’s designed so that a 10 percent optical shrink will enable the half-node of 28 nm. Today, Jagannathan said, a 32 nm low-power (LP) process design kit (PDK) is available in a beta release, and a 28 nm LP PDK is available in an alpha release. IBM has been providing multi-project wafers (MPWs) to customers and partners including ARM and Cadence.

Rob Aitken, R&D fellow at ARM, noted that a physical IP library for the 32/28 nm HKMG process is available for download now. It includes 12 memory compilers, logic libraries, and new multi-channel libraries. The multi-channel libraries make it possible to reduce leakage by using cells that have slightly longer gate lengths. It’s an alternative to the use of high voltage-threshold cells, which can reduce performance.

“The HKMG process is really quite different from previous processes,” Aitken noted. As such, ARM and the Common Platform worked together on design rules, manufacturability, and the library itself. Aitken said ARM has had five tapeouts with the Common Platform 32 nm process, and one 28 nm tapeout. These test chips made it possible to demonstrate early collaboration and to work on design rules.

ARM also used the test chips to run feasibility studies. Engineers found that the 32 nm LP process is able to attain frequencies in the GHz range on critical paths at a nominal operating point.

Vassilios Gerousis, senior architect at Cadence, discussed two 32 nm test chips that Cadence developed with IBM, as described in a previous blog. One let Cadence develop a CMP model, and showed that the 32 nm process has less relative copper loss than 45 nm but higher variability. Another showed that the random variation is large compared to stress, which is a systematic variation. Results may change as the process matures, he noted.

Gerousis noted that Cadence has focused on several areas related to 32 nm, including advanced layout rules, a high-frequency router option to NanoRoute, manufacturing awareness, and the ability to handle large designs. “32 nm is really a breakthrough in terms of layout rules. The number of layout rules is tremendous, and the impact on layout tools is also large,” he noted. NanoRoute is “100 percent compatible” with these layout rules, he said, and the Cadence Virtuoso Space-Based Router supports 32/28 nm layout rules as well. To help with random variations, Cadence is supporting statistical design for timing, signal integrity and leakage.

Panel moderator Ana Molnar Hunter, vice president of foundry for Samsung Semiconductor, closed the panel by stating that “we’re seeing tremendous customer interest in this technology because of the advantages HKMG brings to customers. There’s a lot of excitement and a lot of built-up demand.” Indeed, a full room for an early morning breakfast panel is itself a sign of interest. Designing in a new process node is never easy, but it appears that those who want to move forward will find plenty of ecosystem support.

Richard Goering

Where’s The “You” In The OVM?

Adam Sherilog — Tue, 27 Oct 2009 15:00:00 GMT

Cadence and Mentor have dedicated teams to the development and support of the OVM and you, our user community, have literally tens of thousands of developers dedicated to developing reusable VIP with it. But where do “you” and the OVM meet?

Sometimes the “you” is obvious – the OVM World Forum. With 1100+ unique threads and 4500+ posts, the OVM Forum is by far the most active testbench and reuse site. Every day users interact with the Cadence/Mentor development and support teams, as well as others in the OVM ecosystem, in an open community. Topics range from beginner questions, to enhancement and bug requests, to OVM contributions support, and beyond. Combined with trade-show presentations and webinars, the forums are by far the most public, open face of a testbench methodology.

Speaking of OVM contributions, this is another area on OVM World that is about “you” in a big way. If you have ideas for extensions to the OVM, contribute them! They will be given full consideration for inclusion in future releases. In the meantime, “you” can all share each other’s great ideas.

And sometimes the “you” is less obvious, but may be even more mission-critical. Because your OVM experience depends in part on the methodology/library and in part on the tool suite, some enhancements and bug requests are reported directly to the EDA vendors supporting and developing the OVM solutions. In the case of Mentor and Cadence, we use these reports to fix bugs in the OVM source code. Since these are often accompanied by customer-proprietary examples the bug reports themselves are retained by each EDA provider, but we do exchange simplified examples so that we can jointly produce OVM updates. This effort results in two benefits for OVM users – responses within contractual support timelines to assure the success of their critical projects and bug-fix updates to the OVM downloads. Cadence and Mentor produced two updates to the OVM 2.0 release using this process and a third one – OVM 2.0.3 – is coming in November.

And we can’t forget the OAG – the OVM Advisory Group. This organization of OVM users provides direct guidance for the OVM, and the member companies are publicly identified. The OVM roadmap, presented on the floor of DAC in July and available on OVM World, is a direct result of the OAG. This group will expand over time so that more of “you” can participate directly.

So where is the “you” in the OVM? It’s everywhere – in the public face of OVM World and in the private relationship users have with their EDA partners.

=Adam Sherilog

Things You Didn't Know About Virtuoso: ViVA

stacyw — Tue, 27 Oct 2009 13:00:00 GMT

Sorry I've been missing from this space for so long. I've been busily working on a number of projects to try to help get the word out about all the features I have been (and will be) blogging about. I've also been becoming an expert on making video demos, some of which I'll try to feature here too. Ask your Cadence rep about the new VSE L/XL and ADE XL/GXL interactive Quick Start Guides. (If they don't know what you're talking about, have them contact me...)

The next tool I'd like to take up is ViVA and I thought I'd try using sort of a "Top 3" format and see how that works.

As I realized during a customer presentation earlier this week, the first "Thing You Didn't Know About" ViVA is:

1. What is this "ViVA" thing of which you speak?

Yes, indeed, it suddenly occurred to me that if you use ADE, you'd never know that the waveform viewer is now called "ViVA". Someone at Cadence spent all that time coming up with a cute acronym and no one even knows about it unless they run the tool stand-alone (the executable is "viva") or access the documentation (perish the thought...).

Anyway, ViVA stands for Virtuoso Visualization and Analysis Tool and it consists of the Graph Windows, Calculator and Results Browser you use to display waveforms and make measurements after you run your simulations. Pretty important tasks and, yes, I know, features that many, many people feel extraordinarily strongly about.

So allow me to try to point out some of the little things that just might help you feel enthusiastic about using ViVA.

2. I've got all these waveforms on top of each other. How do I sort out this pile of spaghetti?

Don't worry. There are a lot of easy ways to do this.

First, you'll want to start by figuring out which signal is which. Hold down the "Alt" key over each trace and you'll see the name of the waveform as well as the name of the database file it came from. This can be especially handy for parametric sweeps, when you want to find out which sweep value goes with each curve.

Now, one way to quickly straighten things out is to change to strip mode. (Strip mode is where each waveform is plotted in its own little strip, and all the strips share a common X-axis). To do this, click on the 4th icon from the left at the top of the window, called "Strip Chart Mode" (or choose Axis->Strips from the menu). Voila! Lots of skinny little graphs.

Another way to clean up the graph is to move waveforms to other windows or subwindows. You can do this by clicking on a trace to select (or hold Ctrl and click to select multiple traces). You'll know something is selected if it turns green. Then click on the 6th or 7th icon from the left at the top of the window to move the traces to a new subwindow or a new window. You can also use the Trace->New Graph menu to choose whether you want to do a copy or move operation.

Regardless of whether you are in strip mode or not, did you know that you can drag traces around and drop them in other places to move them? You can rearrange strips in strip chart mode (drop the waveform in between 2 other strips), or you can drag one or more traces between subwindows or windows.

Did you know that Ctrl-X, Ctrl-C and Ctrl-V also work to cut, copy and paste respectively, just like in many other applications?

3. Is there a way to see where the actual simulation timepoints are?

Of course there is. (I wouldn't be writing about it if the answer was "no", now would I?). Just double-click on the trace to bring up the Trace Attributes form. Now, at the end of the line that says "Symbols", click the "Show" checkbox. Then, in the drop-down box next to it, select "All Points" and click OK. This can sometimes help you understand why the waveforms look the way they do.

Worth 1000 words

As they say, watching this in action might help you more than reading about, so please watch this short video showing these and other features in action. Also, click here for another video describing how to change the default colors for waveform plotting from ADE.

If the video fails to play click here.

Stacy Whiteman