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What's Good About Optical Wiring On PCBs? See How Allegro PCB Editor Makes This Happen!
By Gerald "Jerry" Grzenia
on March 18, 2010
This week, I'm taking a brief break from the usual PCB solution/product technical discussions and focusing on a very interesting capability used with the Cadence Allegro PCB Editor product. You can read all the details from this article - Integrated...
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Filed under: PCB design, Allegro, PCB Editor, OPCB, Optical Wiring
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SystemC AMS – A New Proposal For Mixed-Signal Verification
By Richard Goering
on March 18, 2010
In an effort driven by European semiconductor companies and universities, the Open SystemC Initiative ( OSCI ) last week announced the first version of the SystemC analog/mixed-signal language standard, AMS 1.0. Since Cadence is the industry leader in...
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Filed under: Industry Insights, SystemC, OSCI, Virtuoso, Mixed-Signal, AMS, Incisive
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Built-in Message Logging – Part 2 of 2
By Team Specman
on March 17, 2010
[Team Specman welcomes back guest blogger, Michael Avery from our Services Group in the UK] Building on the Part 1 introduction to Specman’s messaging built-in infrastructure , allow me to share some tips on how to programmatically control and scale...
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Filed under: Functional Verification, e, Specman, Aspect Oriented Programming, AOP, debug, Funcional Verification
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ARM AMBA 4 Protocol And VIP – A Closer Look
By Richard Goering
on March 17, 2010
ARM last week announced the first phase of its AMBA 4 specification, and Cadence simultaneously released Incisive verification IP (VIP) for the e language and SystemVerilog. So why is ARM releasing AMBA 4, what's in the two phases, and what's...
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Filed under: Industry Insights, ARM, specman, Incisive, VIP, AMBA, AMBA 4
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UVM = OVM 2.1: Even Better!
By Tom Anderson
on March 16, 2010
Since I'm not a member of the Accellera VIP TSC, I did not attend the 2.5-day face-to-face meeting held last week in Massachusetts. But with the steady stream of tweets coming from several of those who did attend, I almost felt as if I were there...
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Filed under: Functional Verification, OVM, uvm, Accellera VIP TSC
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Bringing MEMS Design To The Mainstream
By Richard Goering
on March 15, 2010
Micro-electrical mechanical systems ( MEMS ) have been around for years, and have found their way into high-volume applications such as automobile air bag controllers, GPS systems, and inkjet print heads. But MEMS devices such as accelerometers, gyroscopes...
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Filed under: Industry Insights, TMSC, Virtuoso, PDK, Coventor, MEMS
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Built-in Message Logging – Part 1 of 2
By Team Specman
on March 11, 2010
[Team Specman welcomes guest blogger Michael Avery, from our Services Group in the UK] Messaging is important for two main reasons: It is essential for debugging It can greatly impact simulation performance This is why Specman has a messaging infrastructure...
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Filed under: Functional Verification, e, Specman, AOP, IES-XL, tech tips
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What's Good AMS Simulator’s Probing? Check Out The SPB16.3 Release!
By Gerald "Jerry" Grzenia
on March 10, 2010
You'll need to check into the nifty new probe capabilities in the SPB16.3 Allegro AMS Simulator release These enhancements will improve your experience with analyzing simulation results especially for dense designs. These features include: Easy to...
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Filed under: PCB design, Allegro, AMS simulator, SPB 16.3, AMS
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Signoff-Driven Implementation = Consistent and Convergent = Predictable and Efficient
By Michael Jacobs
on March 10, 2010
Digital designs are reaching 10's of millions of instances, which makes efficiency of the overall digital implementation and signoff flow critical to ensure predictability in the design schedule. A major stumbling block that can be a real threat to...
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Filed under: Digital Implementation, Signoff Analysis, static timing analysis, Early Rail Analysis, dynamic rail analysis, power analysis, SI analysis, signal integrity, noise analysis, timing system, Multi-Core and Parallel rocessing, timing convergence, Timing Constraints, Timing analysis, Extraction, OCV, Statistical, signoff
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Things You Didn't Know About Virtuoso: IC 6.1.4 ADE Enhancements
By Stacy Whiteman
on March 10, 2010
I'm not going to beat around the bush here. I could tell you about all the things that are new in ADE (Analog Design Environment) in IC 6.1.4. I could tell you about the fact that the individual subwindows are now resizeable, rearrangeable (is that...
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Filed under: Custom IC Design, Virtuoso, IC 6.1.4, Virtuoso Analog Design Environment
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