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Five-Minute Tutorial: Change The Background Color Of EDI
By Kari Summers
on February 08, 2012
Today's tutorial could probably be called a One-Minute Tutorial, since it's so quick. This is something that came across our internal expert alias, and I figured it's something that most people may not know about. Did you know that you can... Read more »
Filed under: Digital Implementation, encounter, EDI, five minute tutorial, background color, changing color, color
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The Zynq Virtual Platform: Not Just for Pre-Silicon
By Jason Andrews
on February 07, 2012
One of the biggest misconceptions about Virtual Platforms is that they are only useful for pre-silicon software development, and once a chip and board is ready they are quickly discarded. Even after boards are available, Virtual Platforms are valuable... Read more »
Filed under: embedded software, linux, SystemC, virtual platforms, virtual prototypes, Virtual System Platform, Zynq, Zynq-7000', Watchdog Timer, pre-silicon, post-silicon
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What's Good About Property Changes in DEHDL? The Secret's in the 16.5 Release!
By Gerald "Jerry" Grzenia
on February 07, 2012
In the 16.5 release, all connectivity changes are stored in the hierarchical block directly in Design Entry HDL (DEHDL). Connectivity changes are basically additions or modifications of components, nets, and pin-net connections. The behavior remains the... Read more »
Filed under: Design Entry HDL, ConceptHDL, Constraint Manager, Allegro, Schematic, PCB, Design Entry, Allegro Design Entry, design, SPB16.5, Allegro 16.5, hierarchy, hierarchical schematics, flat schematics, electrical constraints, uprev, property changes
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Customer, Partner DFM Concerns Spur New Methodologies
By Richard Goering
on February 07, 2012
Design for manufacturing (DFM) may not be as "hot" a topic as it was a few years ago - when there were many independent DFM companies - but foundries and chip design companies are in fact very concerned about DFM at 28nm and below. Some of those... Read more »
Filed under: Industry Insights, lithography, DFM, CMP, IP, Freescale, Design, GlobalFoundries, Cambridge, variability, 20nm, Samsung, manufacturing, foundries, LDE, LEA, design for manufacturability, layout-dependent effects, SPIE, hotspot, SPIE 2012, hot spot, Litho Electrical Analyzer, SPIE papers, Hurat, 28m, printability
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Does Substrate Biasing Have a Future?
By Pete Hardee
on February 06, 2012
At Cadence, we often get asked about various low-power design techniques: how well they work, what are the implementation and verification issues associated with them, and how effective they are at various process nodes. As a general trend we see aggressive... Read more »
Filed under: low-power, PSO, library, power gating, Encounter, power shut-off, low-power design, Substrate bias, body bias, reverse bias, biasing
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Webinar Report: New Methodology Revs Up Code Coverage Analysis
By Richard Goering
on February 06, 2012
Most IC verification teams use code coverage as signoff criteria, but they often have limited information about unreachable code. A new "case-splitting" methodology, described in a recently archived webinar, shows how a technique based on formal... Read more »
Filed under: Industry Insights, verification, Freescale, Metric-driven verification, Functional Verification, Formal Analysis, webinar, formal verification, coverage, coverage metrics, code coverage, case splitting, coverage holes, dead code, case-splitting
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