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Requirement for use of TSMC Library Complete Views:
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Standard cell libraries
40nm | 45nm | 65nm | 90nm | 130nm | 150nm
TechnologyProcess nameLibrary nameDescriptionAvailabilityComplete View
40nmCLN40LPTCBN40LPBWP
TSMC 40nm Logic Low-Power Standard-Vt, 9-Track, Standard Cell Library. Includes level shifter and isolation cell for multi-vdd designs.
Release 110cFront Complete
TCBN40LPBWPHVT
TSMC 40nm Logic Low-Power High-Vt, 9-Track, Standard Cell Library. Includes level shifter and isolation cell for multi-vdd designs.
Release 110cFront Complete
TCBN40LPBWPLVT
TSMC 40nm Logic Low-Power Low-Vt, 9-Track, Standard Cell Library. Includes level shifter and isolation cell for multi-vdd designs.
Release 110cFront Complete
TCBN40LPBWPCG
TSMC 40nm Logic Low-Power Standard-Vt, 9-Track, Coarse-Grain Standard Cell Library. Includes retention flip-flops and AON cells.
Release 120aFront Complete
TCBN40LPBWPCGHVT
TSMC 40nm Logic Low-Power High-Vt, 9-Track, Coarse-Grain Standard Cell Library. Includes retention flip-flops and AON cells.
Release 120aFront Complete
TCBN40LPBWPCGLVT
TSMC 40nm Logic Low-Power Low-Vt, 9-Track, Coarse-Grain Standard Cell Library. Includes retention flip-flops and AON cells.
Release 110bFront Complete
TCBN40LPBWP12T
TSMC 40nm Logic Low-Power Standard-Vt, 12-Track, Standard Cell Library. Also includes level shifter and isolation cell for multi-vdd designs.
Release 120cFront Complete
TCBN40LPBWP12THVT
TSMC 40nm Logic Low-Power High-Vt, 12-Track, Standard Cell Library. Also includes level shifter and isolation cell for multi-vdd designs.
Release 120cFront Complete
TCBN40LPBWP12TLVT
TSMC 40nm Logic Low-Power Low-Vt, 12-Track, Standard Cell Library. Also includes level shifter and isolation cell for multi-vdd designs.
Release 120cFront Complete
TCBN40LPBWP12TCG
TSMC 40nm Logic Low-Power Standard-Vt, 12-Track, Coarse-Grain Standard Cell Library. Includes retention flip-flops and AON cells.
Release 110aFront Complete
TCBN40LPBWP12TCGHVT
TSMC 40nm Logic Low-Power High-Vt, 9-Track, Coarse-Grain Standard Cell Library. Includes header/footer power switches, retention flip-flops and AON cells.
Release 110aFront Complete
TCBN40LPBWP12TCGLVT
TSMC 40nm Logic Low-Power Low-Vt, 12-Track, Coarse-Grain Standard Cell Library. Includes retention flip-flops and AON cells.
Release 110aFront Complete
45nmCLN45GSTCBN45GSBWP
TSMC N45GS(=N45G) 9-Track Standard-Vt Std Cell Library. Includes level shifters and isolation cells for multi-Vdd designs.
Release 120aFront Complete
TCBN45GSBWPHVT
TSMC N45GS(=N45G) 9-Track High-Vt Std Cell Library. Includes level shifters and isolation cells for multi-Vdd designs.
Release 120aFront Complete
TCBN45GSBWPLVT
TSMC N45GS(=N45G) 9-Track Low-Vt Std Cell Library. Includes level shifters and isolation cells for multi-Vdd designs.
Release 120aFront Complete
TCBN45GSBWP12T
TSMC N45GS(=N40G) 12-Track Low-Vt Std Cell Library. Includes level shifters and isolation cells for multi-Vdd designs.
Release 110aFront Complete
TCBN45GSBWP12THVT
TSMC N45GS(=N40G) 12-Track High-Vt Std Cell Library. Includes level shifters and isolation cells for multi-Vdd designs.
Release 110aFront Complete
TCBN45GSBWP12TLVT
TSMC N45GS(=N40G) 12-Track Standard-Vt Std Cell Library. Includes level shifters and isolation cells for multi-Vdd designs.
Release 110aFront Complete
TCBN45GSBWPCG
TSMC N45GS(=N45G) 9-Track Coarse-Grain Standard-Vt Std Cell Library. Includes Retention Flip-Flop, AON Cell
Release 110aFront Complete
TCBN45GSBWPCGHVT
TSMC N45GS(=N45G) 9-Track Coarse-Grain Standard-Vt Std Cell Library. Includes Retention Flip-Flop, AON Cell
Release 110aFront Complete
TCBN45GSBWPCGLVT
TSMC N45GS(=N45G) 9-Track Coarse-Grain Standard-Vt Std Cell Library. Includes Retention Flip-Flop, AON Cell
Release 100aFront Complete
TCBN45GSBWP12TCG
TSMC N45GS(=N45G) 9-Track Coarse-Grain Standard-Vt Std Cell Library. Includes Retention Flip-Flop, AON Cell
Release 100aFront Complete
TCBN45GSBWP12TCGHVT
TSMC N45GS(=N45G) 9-Track Coarse-Grain Standard-Vt Std Cell Library. Includes Retention Flip-Flop, AON Cell
Release 100aFront Complete
TCBN45GSBWP12TCGLVT
TSMC N45GS(=N45G) 9-Track Coarse-Grain Standard-Vt Std Cell Library. Includes Retention Flip-Flop, AON Cell
Release 100aFront Complete
65nmCLN65LPTCBN65LPHPBWPLVT
TSMC 65nm Logic Low Power Process (1P9M, core 1.2V), 0.20um x-pitch, Low-Vt, total 847 cells (include 695 base cells, 12 level shifter cells, 8 isolation cells, 10 filler cells, and 52 ECO cells), 10-tracks, Tapless Raw gate density = 769Kgate/mm^2, Support multi-Vdd design , low-voltage range is 1.0V +/- 10%
Release 140bFront Complete
TCBN65LPHPBWPHVT
TSMC 65nm Logic Low Power Process (1P9M, core 1.2V), 0.20um x-pitch, Low-Vt, total 847 cells (include 695 base cells, 12 level shifter cells, 8 isolation cells, 10 filler cells, and 52 ECO cells), 10-tracks, Tapless Raw gate density = 769Kgate/mm^2, Support multi-Vdd design , low-voltage range is 1.0V +/- 10%
Release 140bFront Complete
TCBN65LPHPBWP
TSMC 65nm Logic Low Power Process (1P9M, core 1.2V), 0.20um x-pitch, Standard-Vt, total 847 cells (include 695 base cells, 12 level shifter cells, 8 isolation cells, 10 filler cells, and 52 ECO cells), 10-tracks, Tapless Raw gate density = 769Kgate/mm^2, Support multi-Vdd design , low-voltage range is 1.0V +/- 10%
Release 140bFront Complete
TCBN65LP
TSMC 65nm Logic Low-Power 1.2/2.5V process, 0.20um x-pitch, Standard Vt, total 855 cells (include 694base cells, 28 multi-voltage cells, 70 clock cells, 11 filler cells and 52 ECO cells), 9-tracks, Raw gate density = 854 Kgate/mm^2, Support multi-Vdd design , low-voltage range is 0.8V +/- 10%, CCS timing/noise model is included
Release 140cFront Complete
TCBN65LPCG
TSMC 65nm Low-power process (1P9M, core 1.2V), Coarse-grain MTCMOS library, Standard-Vt total 20 cells, Include special cell for 1) power switch header cell, 2) retention flip-flop cell, 3) always on cell
Release 140bFront Complete
TCBN65LPCGHVT
TSMC 65nm Low-power process (1P9M, core 1.2V), Coarse-grain MTCMOS library, High-Vt, Include special cell for 1) power switch header cell, 2) retention flip-flop cell, 3) always on cell
Release 140bFront Complete
TCBN65LPCGLVT
TSMC 65nm Low-power process (1P9M, core 1.2V), Coarse-grain MTCMOS library, Low-Vt , Include special cell for 1) power switch header cell, 2) retention flip-flop cell, 3) always on cell
Release 140bFront Complete
TCBN65LPHVT
TSMC 65nm Logic Low-Power 1.2/2.5V process, 0.20um x-pitch, High Vt, total 855 cells (include 694base cells, 28 multi-voltage cells, 70 clock cells, 11 filler cells and 52 ECO cells), 9-tracks, Raw gate density = 854 Kgate/mm^2, Support multi-Vdd design , low-voltage range is 0.8V +/- 10%, CCS timing/noise model is included
Release 140cFront Complete
TCBN65LPLVT
TSMC 65nm Logic Low-Power 1.2/2.5V process, 0.20um x-pitch, Low Vt, total 855 cells (include 694base cells, 28 multi-voltage cells, 70 clock cells, 11 filler cells and 52 ECO cells), 9-tracks, Raw gate density = 854 Kgate/mm^2, Support multi-Vdd design , low-voltage range is 0.8V +/- 10%, CCS timing/noise model is included
Release 140cFront Complete
TCBN65LPBWP12T
TSMC 65nm Logic Low-Power 1.2/2.5V process, 0.20um x-pitch, Standard-Vt, 12-track, Raw gate density = 854 Kgate/mm^2, Support multi-Vdd design , low-voltage range is 0.8V +/- 10%
Release 140cFront Complete
TCBN65LPBWP12THVT
TSMC 65nm Logic Low-Power 1.2/2.5V process, 0.20um x-pitch, High-Vt, 12-track, Raw gate density = 854 Kgate/mm^2, Support multi-Vdd design , low-voltage range is 0.8V +/- 10%
Release 140cFront Complete
TCBN65LPBWP12TLVT
TSMC 65nm Logic Low-Power 1.2/2.5V process, 0.20um x-pitch, Low-Vt, 12-track, Raw gate density = 854 Kgate/mm^2, Support multi-Vdd design , low-voltage range is 0.8V +/- 10%
Release 140cFront Complete
TCBN65LPG
TSMC 65nm Logic LP-based TGO with dual-core 1p9m 1/1.2/2.5V process, 0.20um x-pitch, Standard Vt, total 846 cells (include 816 base cells, 12 level shifter cells, 8 isolation cells and 10 filler cells), 9-tracks, Raw gate density = 854 Kgate/mm^2, Support multi-Vdd design , low-voltage range is 0.8V +/- 10%, CCS timing/noise model is included
Release 130bFront Complete
TCBN65LPGHVT
TSMC 65nm Logic LP-based TGO with dual-core 1p9m 1/1.2/2.5V process, 0.20um x-pitch, High-Vt, total 846 cells (include 816 base cells, 12 level shifter cells, 8 isolation cells and 10 filler cells), 9-tracks, Raw gate density = 854 Kgate/mm^2, Support multi-Vdd design , low-voltage range is 0.8V +/- 10%, CCS timing/noise model is included
Release 130bFront Complete
TCBN65LPBWP7T
TSMC 65nm Logic 1.2V/2.5V Low power process (1P9M, core 1.2V), Standard Vt, 7-track library. 0.20um x-pitch, total 644 cells (include 620 base cells, 9 level shifter cells, 6 isolation cells and 8 filler cells, 1 tapcell), Raw gate density = 1020 Kgate/mm^2, Support multi-Vdd design , low-voltage range is 1.0V +/- 10%, CCS timing model is included
Release 141aFront Complete
TCBN65LPBWP7THVT
TSMC 65nm Logic 1.2V/2.5V Low power process (1P9M, core 1.2V), High Vt, 7-track library. 0.20um x-pitch, total 644 cells (include 620 base cells, 9 level shifter cells, 6 isolation cells and 8 filler cells, 1 tapcell), Raw gate density = 1020 Kgate/mm^2, Support multi-Vdd design , low-voltage range is 1.0V +/- 10%, CCS timing model is included
Release 141aFront Complete
TCBN65LPBWP7TLVT
TSMC 65nm Logic 1.2V/2.5V Low power process (1P9M, core 1.2V), Low Vt, 7-track library. 0.20um x-pitch, total 644 cells (include 620 base cells, 9 level shifter cells, 6 isolation cells and 8 filler cells, 1 tapcell), Raw gate density = 1020 Kgate/mm^2, Support multi-Vdd design , low-voltage range is 1.0V +/- 10%, CCS timing model is included
Release 141aFront Complete
TCBN65LPBWP12TCG
TSMC 65nm Low-power process (1P9M, core 1.2V), Coarse-grain MTCMOS library, Standard-Vt total 20 cells, Include special cell for 1) power switch header cell, 2) retention flip-flop cell, 3) always on cell
Release 140aFront Complete
TCBN65LPBWP12TCG
TSMC 65nm Low-power process (1P9M, core 1.2V), Coarse-grain MTCMOS library, High-Vt total 20 cells, Include special cell for 1) power switch header cell, 2) retention flip-flop cell, 3) always on cell
Release 140aFront Complete
TCBN65LPBWP12TCGLVT
TSMC 65nm Low-power process (1P9M, core 1.2V), Coarse-grain MTCMOS library, Low-Vt total 20 cells, Include special cell for 1) power switch header cell, 2) retention flip-flop cell, 3) always on cell
Release 140aFront Complete
TCBN65LPDF
TSMC 65LP process (core voltage = 1.0V), dual-FF,Standard-VT, 0.20um x-pitch, 9-tracks, Raw gate density = 854 Kgate/mm^2
Release 140aFront Complete
TCBN65LPDFHVT
TSMC 65LP process (core voltage = 1.0V), dual-FF,Standard-VT, 0.20um x-pitch, 9-tracks, Raw gate density = 854 Kgate/mm^2
Release 140aFront Complete
TCBN65LPDFLVT
TSMC 65LP process (core voltage = 1.0V), dual-FF,Standard-VT, 0.20um x-pitch, 9-tracks, Raw gate density = 854 Kgate/mm^2
Release 140aFront Complete
TCBN65LPHPBWPCG
TSMC 65nm Low-power process (1P9M, core 1.2V), Coarse-grain MTCMOS library, Standard-Vt . Include special cell for 1) power switch header & footer cells, 2) retention flip-flop cell, 3) always on cell
Release 140aFront Complete
TCBN65LPHPBWPCGHVT
TSMC 65nm Low-power process (1P9M, core 1.2V), Coarse-grain MTCMOS library, High-Vt . Include special cell for 1) power switch header & footer cells, 2) retention flip-flop cell, 3) always on cell
Release 140aFront Complete
TCBN65LPHPBWPCGLVT
TSMC 65nm Low-power process (1P9M, core 1.2V), Coarse-grain MTCMOS library, Low-Vt . Include special cell for 1) power switch header & footer cells, 2) retention flip-flop cell, 3) always on cell
Release 140aFront Complete
TCBN65LPHVTCG
TSMC 65nm Low-power process (1P9M, core 1.2V), Coarse-grain MTCMOS library, High-Vt total 20 cells, Include special cell for 1) power switch header cell, 2) retention flip-flop cell, 3) always on cell
Release 120cFront Complete
TCBN65LPLVTCG
TSMC 65nm Low-power process (1P9M, core 1.2V), Coarse-grain MTCMOS library, Low-Vt total 20 cells, Include special cell for 1) power switch header cell, 2) retention flip-flop cell, 3) always on cell
Release 120cFront Complete
CLN65GPTCBN65GPLUSHPBWPLVT
TSMC 65nm Logic 1.0V/1.8V GPLUS process (1P9M, core 1.0V), 0.20um x-pitch, Low-Vt, total 847 cells (include 694 base cells, 20 Multi-volgate cells, 70 clock cells, 1 TAP cell,10 filler cells, and 52 ECO cells), 10-tracks, Tapless cell layout structure, Raw gate density = 769Kgate/mm^2, Support multi-Vdd design , low-voltage range is 0.8*Vdd +/- 10%
Release 140aFront Complete
TCBN65GPLUSHPBWPHVT
TSMC 65nm Logic 1.0V/1.8V GPLUS process (1P9M, core 1.0V), 0.20um x-pitch, High-Vt, total 847 cells (include 694 base cells, 20 Multi-volgate cells, 70 clock cells, 1 TAP cell,10 filler cells, and 52 ECO cells), 10-tracks, Tapless cell layout structure, Raw gate density = 769Kgate/mm^2, Support multi-Vdd design , low-voltage range is 0.8*Vdd +/- 10%
Release 140aFront Complete
TCBN65GPLUSHPBWP
TSMC 65nm Logic 1.0V/1.8V GPLUS process (1P9M, core 1.0V), 0.20um x-pitch, Standard-Vt, total 847 cells (include 694 base cells, 20 Multi-volgate cells, 70 clock cells, 1 TAP cell,10 filler cells, and 52 ECO cells), 10-tracks, Tapless cell layout structure, Raw gate density = 769Kgate/mm^2, Support multi-Vdd design , low-voltage range is 0.8*Vdd +/- 10%
Release 140aFront Complete
TCBN65GPLUS
TSMC 65nm Logic 1.0V/1.8V GPLUS process (1P9M, core 1.0V),Standard-Vt,9-track.Includes level shifter and isolation cell for multi-vdd designs.
Release 140bFront Complete
TCBN65GPLUSCG
TSMC 65nm Generic-plus process (1P9M, core 1.0V), Coarse-grain MTCMOS library, Standard-Vt
Release 140bFront Complete
TCBN65GPLUSCGHVT
TSMC 65nm Generic-plus process (1P9M, core 1.0V), Coarse-grain MTCMOS library, High-Vt
Release 140bFront Complete
TCBN65GPLUSCGLVT
TSMC 65nm Generic-plus process (1P9M, core 1.0V), Coarse-grain MTCMOS library, Low-Vt
Release 140bFront Complete
TCBN65GPLUSHVT
TSMC 65nm Logic 1.0V/1.8V GPLUS process (1P9M, core 1.0V),High-Vt,9-track.Includes level shifter and isolation cell for multi-vdd designs.
Release 140bFront Complete
TCBN65GPLUSLVT
TSMC 65nm Logic 1.0V/1.8V GPLUS process (1P9M, core 1.0V),Low-Vt,9-track.Includes level shifter and isolation cell for multi-vdd designs.
Release 140bFront Complete
90nmCLN90GTCBN90G
General Purpose, Logic Library
Release 121aFront Complete
TCBN90GHVT
General Purpose, High Threshold Voltage
Release 121aFront Complete
TCBN90GLVT
General Purpose, Low Threshold Voltage
Release 121aFront Complete
TCBN90GHP
TSMC 90nm logic 1P9M generic standard cell library. 0.28um x-pitch, normal-Vt, 9-tracks. Raw gate density = 436 KGate/mm^2, Support multi-Vdd design (include level shifter cell and isolation cell inside)
Release 210bFront Complete
TCBN90GHPCG
Coarse-grain MTCMOS library, Standard-Vt total 20 cells, Include special cell for 1) power switch header cell, 2) retention flip-flop cell, 3) always on cell
Release 150aFront Complete
TCBN90GHPCGHVT
Coarse-grain MTCMOS library, high-Vt total 20 cells, Include special cell for 1) power switch header cell, 2) retention flip-flop cell, 3) always on cell
Release 150aFront Complete
TCBN90GHPCGLVT
Coarse-grain MTCMOS library, Low-Vt total 20 cells, Include special cell for 1) power switch header cell, 2) retention flip-flop cell, 3) always on cell
Release 150aFront Complete
TCBN90GHPHVT
TSMC 90nm logic 1P9M generic standard cell library. 0.28um x-pitch, high-Vt, 9-tracks. Raw gate density = 436 KGate/mm^2, Support multi-Vdd design (include level shifter cell and isolation cell inside)
Release 210bFront Complete
TCBN90GHPHVTWB
Generic process (1P9M,1.0v/1.8v, 2.5v, 3.3v), 0.28um x-pitch, High-Vt
Release 151aFront Complete
TCBN90GHPLVT
TSMC 90nm logic 1P9M generic standard cell library. 0.28um x-pitch, Low-Vt, 9-tracks. Raw gate density = 436 KGate/mm^2, Support multi-Vdd design (include level shifter cell and isolation cell inside)
Release 210bFront Complete
TCBN90GHPLVTWB
Generic process (1P9M,1.0v/1.8v, 2.5v, 3.3v), 0.28um x-pitch, Low-Vt
Release 151aFront Complete
TCBN90GHPOD
Overdrive Logic Library
Release 150bFront Complete
TCBN90GHPODHVT
Overdrive, High Threshold Voltage
Release 150bFront Complete
TCBN90GHPODLVT
Overdrive, Low Threshold Voltage
Release 150bFront Complete
TCBN90GHPWB
Generic process (1P9M,1.0v/1.8v, 2.5v, 3.3v), 0.28um x-pitch, Standard-Vt
Release 151aFront Complete
TCBN90GOD
General Purpose, Overdrive Logic Library
Release 121aFront Complete
TCBN90GODHVT
General Purpose, Overdrive, High Threshold Voltage
Release 121aFront Complete
TCBN90GODLVT
General Purpose, Overdrive, High Performance
Release 121aFront Complete
TCBN90GECO
TSMC 90nm Logic (1P9M, 1.0V/1.8V, 2.5V, 3.3V) ECO library. This library is intended to serve logic changes with metals only ECO after first tape-out without having to touch base layers of POLY layer and below.
Release 121aFront Complete
TCBN90GHVTECO
TSMC 90nm Logic (1P9M, 1.0V/1.8V, 2.5V, 3.3V) ECO library. 0.32um x-pitch, high-vt, This library is intended to serve logic changes with metals only ECO after first tape-out without having to touch base layers of POLY layer and below.
Release 121aFront Complete
TCBN90GLVTECO
TSMC 90nm Logic (1P9M, 1.0V/1.8V, 2.5V, 3.3V) ECO library. 0.32um x-pitch, low-vt, This library is intended to serve logic changes with metals only ECO after first tape-out without having to touch base layers of POLY layer and below.
Release 121aFront Complete
TCBN90GODECO
TSMC 90nm Logic (1P9M, 1.0V/1.8V, 2.5V, 3.3V) ECO library. 0.32um x-pitch, over-drive 1.2V, This library is intended to serve logic changes with metals only ECO after first tape-out without having to touch base layers of POLY layer and below.
Release 121aFront Complete
TCBN90GODHVTECO
TSMC 90nm Logic (1P9M, 1.0V/1.8V, 2.5V, 3.3V) ECO library. 0.32um x-pitch, high-vt, over-drive 1.2V, This library is intended to serve logic changes with metals only ECO after first tape-out without having to touch base layers of POLY layer and below.
Release 121aFront Complete
TCBN90GODLVTECO
TSMC 90nm Logic (1P9M, 1.0V/1.8V, 2.5V, 3.3V) ECO library. 0.32um x-pitch, low-vt, over-drive 1.2V, This library is intended to serve logic changes with metals only ECO after first tape-out without having to touch base layers of POLY layer and below.
Release 121aFront Complete
TCBN90GBWP7T
TSMC 90nm Logic General Purpose 1.0V/2.5V Process (1P9M, core 1.0V), Standard Vt, 7-track M1 only library. 0.28um x-pitch, total 586 cells (include 562 base cells, 9 level shifter cells, 6 isolation cells and 9 filler cells, 1 tapcell), Raw gate density = 560 Kgate/mm^2, Support multi-Vdd design , low-voltage range is 0.8V+/-10%
Release 210aFront Complete
TCBN90GBWP7THVT
TSMC 90nm Logic General Purpose 1.0V/2.5V Process (1P9M, core 1.0V), High Vt, 7-track M1 only library. 0.28um x-pitch, total 586 cells (include 562 base cells, 9 level shifter cells, 6 isolation cells and 9 filler cells, 1 tapcell), Raw gate density = 560 Kgate/mm^2, Support multi-Vdd design , low-voltage range is 0.8V+/-10%
Release 210aFront Complete
TCBN90GBWP7TLVT
TSMC 90nm Logic General Purpose 1.0V/2.5V Process (1P9M, core 1.0V), Low Vt, 7-track M1 only library. 0.28um x-pitch, total 586 cells (include 562 base cells, 9 level shifter cells, 6 isolation cells and 9 filler cells, 1 tapcell), Raw gate density = 560 Kgate/mm^2, Support multi-Vdd design , low-voltage range is 0.8V+/-10%
Release 210aFront Complete
TPBN90V
Bond Pad Library
Release 210aFront Complete
CLN90LPTCBN90LPHP
TSMC 90nm Low-power process (1P9M,1.2v/2.5v), 0.28um x-pitch, nominal-Vt, total 867 cells(include filler cells), 9-tracks. Raw gate density = 436 KGate/mm^2, Support multi-Vdd design (include level shifter cell and isolation cell inside)
Release 150jFront Complete
TCBN90LPHPCG
Coarse-grain MTCMOS library, Standard-Vt
Release 150fFront Complete
TCBN90LPHPHVT
TSMC 90nm Low-power process (1P9M,1.2v/2.5v), 0.28um x-pitch, high-Vt, total 867 cells(include filler cells), 9-tracks. Raw gate density = 436 KGate/mm^2, Support multi-Vdd design (include level shifter cell and isolation cell inside)
Release 150jFront Complete
TCBN90LPHPHVTCG
Coarse-grain MTCMOS library, High-Vt
Release 150eFront Complete
TCBN90LPHPHVTWB
TSMC 90nm Low-power process (1P9M,1.2v/2.5v), 0.28um x-pitch, High-Vt, total 845 cells (base cell: 805 cells, ECO cell: 32 cells, 7 filler cells + 1 TAP cell), 9-tracks, back-bias library, bias voltage = 0.6V, Raw gate density = 451 Kgate/mm^2
Release 150dFront Complete
TCBN90LPHPLVT
TSMC 90nm Low-power process (1P9M,1.2v/2.5v), 0.28um x-pitch, low-Vt, total 867 cells(include filler cells), 9-tracks. Raw gate density = 436 KGate/mm^2, Support multi-Vdd design (include level shifter cell and isolation cell inside)
Release 150hFront Complete
TCBN90LPHPLVTCG
Coarse-grain MTCMOS library, Low-Vt
Release 150eFront Complete
TCBN90LPHPLVTWB
Low-power process (1P9M,1.2v/2.5v)
Release 150cFront Complete
TCBN90LPHPUHVT
Low Power, High Performance, L-VT
Release 121aFront Complete
TCBN90LPHPWB
Low-power process (1P9M,1.2v/2.5v)
Release 150cFront Complete
TCBN90LPHDBWP
TSMC 90nm Logic 1.2V/2.5V Low power process (1P9M, core 1.2V), Standard Vt, 7-track library. 0.28um x-pitch, total 645 cells (include 620 base cells, 9 level shifter cells, 6 isolation cells and 9 filler cells, 1 tapcell), Raw gate density = 560 Kgate/mm^2, Support multi-Vdd design , low-voltage range is 1.0V +/- 10%
Release 200fFront Complete
TCBN90LPHDBWPULVT
TSMC 90nm Logic 1.2V/2.5V Low power process (1P9M, core 1.2V), Standard Vt, 7-track library. 0.28um x-pitch, total 645 cells (include 620 base cells, 9 level shifter cells, 6 isolation cells and 9 filler cells, 1 tapcell), Raw gate density = 560 Kgate/mm^2, Support multi-Vdd design , low-voltage range is 1.0V +/- 10%
Release 200fFront Complete
TCBN90LPHDBWPHVT
TSMC 90nm Logic 1.2V/2.5V Low power process (1P9M, core 1.2V), High Vt, 7-track library. 0.28um x-pitch, total 645 cells (include 620 base cells, 9 level shifter cells, 6 isolation cells and 9 filler cells, 1 tapcell), Raw gate density = 560 Kgate/mm^2, Support multi-Vdd design , low-voltage range is 1.0V +/- 10%
Release 200fFront Complete
TCBN90LPHDBWPLVT
TSMC 90nm Logic 1.2V/2.5V Low power process (1P9M, core 1.2V), Low Vt, 7-track library. 0.28um x-pitch, total 645 cells (include 620 base cells, 9 level shifter cells, 6 isolation cells and 9 filler cells, 1 tapcell), Raw gate density = 560 Kgate/mm^2, Support multi-Vdd design , low-voltage range is 1.0V +/- 10%
Release 200fFront Complete
TCBN90LPBWP7T
TSMC 90nm Logic 1.2V/2.5V Low power process (1P9M, core 1.2V), Low Vt, 7-track library. 0.28um x-pitch, total 645 cells (include 620 base cells, 9 level shifter cells, 6 isolation cells and 9 filler cells, 1 tapcell), Raw gate density = 560 Kgate/mm^2, Support multi-Vdd design , low-voltage range is 1.0V +/- 10%
Release 210aFront Complete
TCBN90LPBWP7T
TSMC 90nm Logic 1.2V/2.5V Low power process (1P9M, core 1.2V), Low Vt, 7-track library. 0.28um x-pitch, total 645 cells (include 620 base cells, 9 level shifter cells, 6 isolation cells and 9 filler cells, 1 tapcell), Raw gate density = 560 Kgate/mm^2, Support multi-Vdd design , low-voltage range is 1.0V +/- 10%
Release 210aFront Complete
TCBN90LPBWP7THVT
TSMC 90nm Logic 1.2V/2.5V Low power process (1P9M, core 1.2V), Low Vt, 7-track M1 only library. 0.28um x-pitch, total 586 cells (include 562 base cells, 9 level shifter cells, 6 isolation cells and 9 filler cells, 1 tapcell), Raw gate density = 560 Kgate/mm^2, Support multi-Vdd design , low-voltage range is 1.0V +/- 10%
Release 210aFront Complete
TCBN90LPBWP7TLVT
TSMC 90nm Logic 1.2V/2.5V Low power process (1P9M, core 1.2V), High Vt, 7-track M1 only library. 0.28um x-pitch, total 586 cells (include 562 base cells, 9 level shifter cells, 6 isolation cells and 9 filler cells, 1 tapcell), Raw gate density = 560 Kgate/mm^2, Support multi-Vdd design , low-voltage range is 1.0V +/- 10%
Release 210aFront Complete
TPBN90V
Bond Pad Library
Release 210aFront Complete
CLN90GTTCBN90GTHP
GT High Performance
Release 150aFront Complete
TCBN90GTHPHVT
GT High Performance, High Threshold Voltage
Release 150aFront Complete
TCBN90GTHPLVT
GT High Performance, Low Threshold Voltage
Release 150aFront Complete
TPBN90V
Bond Pad Library
Release 210aFront Complete
CLN90HSTPBN90V
Bond Pad Library
Release 210aFront Complete
CLN90LETPBN90V
Bond Pad Library
Release 210aFront Complete
CLN90UPTPBN90V
Bond Pad Library
Release 210aFront Complete
130nmCL013GTCB013GHP
General Purpose High Performance
Release 220aFront Complete
TCB013GHPHVT
High Performance, High Threshold Voltage
Release 220aFront Complete
TCB013GHPLVT
High Performance, Low Threshold Voltage
Release 220aFront Complete
TCB013GHP_ECO
TSMC 0.13um Generic Logic (1P8M, 1.2V/2.5V,3.3V) ECO library. This library is intended to serve logic changes with metals/contacts(vias) only ECO after first tape-out without having to touch base layers of CO layer and below
Release 211aFront Complete
TCB013GHPHVT_ECO
Release 211aFront Complete
TCB013GHPLVT_ECO
TSMC 0.13um Generic Logic (1P8M, 1.2V/2.5V,3.3V) ECO library. Low-Vt, This library is intended to serve logic changes with metals/contacts(vias) only ECO after first tape-out without having to touch base layers of CO layer and below
Release 211aFront Complete
TPZ013GV3
1.2V/3.3V, 5V tolerant, staggered universal standard I/O
Release 220bFront Complete
CL013LVTCB013LVHP
TSMC 0.13um logic 1P8M Low-Voltage High-Performance library, Total 747 + 7 filler cells, 9 tracks, Raw gate density = 196KGate/mm^2
Release 220aFront Complete
TCB013LVHPHVT
Low Voltage, High Performance, High Threshold Voltage
Release 220aFront Complete
TCB013LVHPOD
Low Voltage, High Performance, Overdrive
Release 220aFront Complete
TCB013LVHPODHVT
Low Voltage, High Performance Overdrive, High Threshold
Release 220aFront Complete
TCB013LVHPHVT_ECO
TSMC 0.13um logic 1P8M Low-Voltage ECO library, High-Vt, This library is intended to serve logic changes with metals/contacts(vias) only ECO after first tape-out without having to touch base layers of CO layer and below
Release 211aFront Complete
TCB013LVHPOD_ECO
TSMC 0.13um logic 1P8M Low-Voltage ECO library, Over-drive 1.2V, This library is intended to serve logic changes with metals/contacts(vias) only ECO after first tape-out without having to touch base layers of CO layer and below
Release 211aFront Complete
TCB013LVHPODHVT_ECO
TSMC 0.13um logic 1P8M Low-Voltage ECO library, High-Vt, Over-drive 1.2V, This library is intended to serve logic changes with metals/contacts(vias) only ECO after first tape-out without having to touch base layers of CO layer and below
Release 211aFront Complete
CL013LPTCB013LPHP
Low Power, High Performance
Release 220aFront Complete
TCB013LPHPLVT
Low Power, High Performance, Low Threshold Voltage
Release 220aFront Complete
TCB013LVHP_ECO
TSMC 0.13um logic 1P8M Low-Voltage ECO library This library is intended to serve logic changes with metals/contacts(vias) only ECO after first tape-out without having to touch base layers of CO layer and below
Release 211aFront Complete
150nmCL015GTCB015G
General Purpose logic library
Release 211aFront Complete
TCB015GHD
TSMC 0.15um Generic (1.5v, 1P7M) standard cell library, High-density, 514 cells +7 filler cell, 8 tracks, Raw gate density = 160 KGate/mm2
Release 222aFront Complete
TCB015LV
TSMC 0.15um Low-Voltage Standard cell library 1P7M 1.2V/2.5V,1.2V/3.3V, 9 tracks, total 514 cells + 7 filler cells, Raw gate density = 131 KGate/mm^2
Release 211aFront Complete
CL015LVTCB015LVHD
TSMC 0.15um Low-Voltage Standard cell library 1P7M 1.2V/2.5V,1.2V/3.3V, 8 tracks, High-density, total 514 cells + 7 filler cells, Raw Gate Density = 160K gates/mm^2
Release 222aFront Complete


Standard I/O libraries
45nm | 65nm | 90nm | 130nm
TechnologyProcess nameLibrary nameDescriptionAvailabilityComplete View
45nmCLN45GSTPZN45GSGV18
0.9V/1.8V, 2.5V Tolerant, Staggered Universal Standard I/O
Release 120bFront Complete
TPFN45GSGV2OD3
0.9V/2.5V, over-drive to 3.3V, Staggered Universal Standard I/O
Release 120bFront Complete
TPFN45GSGV18
0.9V/1.8V, fail-safe, Staggered Universal Standard I/O
Release 120bFront Complete
TPBN45V
bond pad library
Release 110bFront Complete
65nmCLN65LPTPBN45V
The N65 bond pad library that contains both staggered and in-line bond pads in particular for TSMC N65 staggered and linear universal I/O libraries.
Release 140aFront Complete
TPDN65LPNV2OD3
1.2/2.5V, over-drive to 3.3V, Regular, Linear Universal Standard I/O
Release 140bFront Complete
90nmCLN90GTPZN90GV3
1. Silicon proven release. 2. Modified RH layer to meet RES.10.g DRC added in version 2.0 design rule
Release 200Front Complete
CLN90LPTPDN90LPNV3
1.2V/3.3V, regular, linear universal standard I/O
Release 220aFront Complete
130nmCL013GTPD013NV3
1.2V/3.3V regular, linear unviersal standard I/O
Release 220dFront Complete
TPD013LPNV
1.5V/3.3V, Regular, Linear Universal Standard I/O
Release 220aFront Complete
CL013LVTPZ013LODGV3
1.0V/3.3V, 5V tolerant, staggered universal standard I/O with core voltage overdriving to 1.2V
Release 220bFront Complete
CL013LPTPD013LPNV3
1.5V/3.3V, Regular, Linear Universal Standard I/O
Release 220bFront Complete