Home > Alliances > Standards & Languages

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Company Location *

Comments: *

Standards & Languages 

One language can't solve all design and verification problems. Different teams use different languages to take advantage of the unique features each one provides. As a leader of open standards, Cadence is dedicated to providing continuous support for a variety of design and verification languages and implementation standards.

For implementation tools, Cadence supports LEF, DEF, GDSII, SDF, and SPEF.

To date, Cadence has donated and made accessible to the industry more than a dozen major proprietary languages, formats, API specifications, and reference implementations, including Verilog, VHDL, SystemC, GDSII, SDF, LEF, DEF, ECSM.

To ensure unified standards for advanced design and verification, and to improve the process of turning specifications into fully implemented standards, Cadence is an active participant in Accellera and IEEE standards committees.

Verilog

Verilog is the incumbent de facto and IEEE standard (IEEE 1364-2001) for RTL design. It has been in widespread use since the 1980's and is supported by all major EDA vendors. It is the basis for most logic synthesis tools and it provides good support for ASIC design and verification of simple and moderately complex chips. The limitations of Verilog became apparent in the late 1990's as the growing complexity of designs mandated better solutions for verification and increased abstraction levels for effective design and modeling. Verilog remains the language of choice for a broad cross-section of today's' designers who are not involved in cutting edge projects or who use it as an implementation language in a Multilanguage design and verification flow.

VHDL

VHDL (IEEE 1076) enjoys a similar position to Verilog in terms of its scope and application to synthesizable design. Its appeal is rooted in its precise semantics and higher level abstraction and it is the language of choice for many design teams. VHDL does continue to evolve with the latest update standardized in 2008 (IEEE 1076-2008).

SystemVerilog

SystemVerilog is an IEEE standard 1800 that expands on base Verilog® language by adding convenience and abstraction extensions for design, assertions, and verification. The new design features enable more efficient design coding through virtual interfaces, generators, enumerated types, and more. The testbench features enable object-oriented programming using dynamic types, randomization, constraints, and more which enables SystemVerilog to be applied to complex verification tasks. After several years of competing methodology, Accellera standardized verification methodology and created a SystemVerilog reference library. The Universal Verification Methodology (UVM) the only open, interoperable, proven, and standardized verification methodology. The UVM is an open-source SystemVerilog class library and methodology that defines a framework for reusable verification IP (VIP) and tests. It is 100% IEEE 1800 SystemVerilog and provides building blocks (objects) and a common set of verification-related utilities. The UVM is released under the Apache 2.0 license, enabling anyone to use UVM libraries for any purpose, including creation of derivative work. The UVM is developed by Accellera and is known to run on Cadence, Mentor Graphics, and Synopsys simulators to facilitate true SystemVerilog interoperability with a standard library and a proven methodology.

Property Specific Language (PSL)

PSL (IEEE 1850) supports Verilog, VHDL, and SystemC. It includes multiple abstraction layers for assertion types ranging from low-level boolean and temporal to higher-level modeling and verification. PSL does continue to evolve and the latest update is the IEEE 1850-2010 standard.

SystemC

SystemC (IEEE 1666) is ideal for transaction level modeling and high performance reference modeling. SystemC can also be synthesized and there is a technical committee of the Accellera Systems Initiative working on a standard language subset for synthesis. Testbenches for SystemC can be written in SystemC, but many product teams choose the Accellera Systems Initiative Universal Verification Methodology (UVM) SystemVerilog and/or e enabling reuse of the tests at the next lower level of abstraction with Verilog and VHDL.

Encryption

Globalization of design has increased the need to exchange intellectual property (IP) among groups in a single company and among companies in a design chain. The IEEE P1735 Recommended Practice for Encryption and Management of Electronic Design Intellectual Property (IP) seeks to standardize the safe interchange of IP. It leverages public key encryption to enable multiple tools in the design chain, from multiple vendors, operate on the intellectual property.