Industry-wide interoperability and reusable verification IP
The Universal Verification Methodology (UVM) is a standard being developed by Accellera for the expressed purpose of fostering universal verification IP (VIP) interoperability. Championed and supported by electronics companies throughout the verification ecosystem, the UVM will increase productivity by eliminating expensive interfacing that slows VIP reuse.
The UVM is based on the Open Verification Methodology (OVM) 2.1.1 release and incorporates some incremental functionality to validate the SourceForge-based development process. This extended functionality comes from the combined strengths of the Verification Methodology Manual (VMM), the OVM, and new technology developed by the Accellera VIP Technical Subcommittee. Along with the base-class library (BCL), the UVM provides two important documents: a reference manual to the APIs in UVM and a user guide suggesting how to apply UVM—both of which originated with the OVM but have been updated for the UVM. Accellera members have tested the UVM on multiple simulators to enable the verification IP developed with it to run universally. The UVM BCL and documentation, along with additional contributions, blogs, and forums, are available immediately for download from
www.uvmworld.org.
The Cadence® “Best UVM” program offers several advantages for UVM users with Cadence Incisive® solutions. Leading this program is the Cadence contribution of the open-source
UVM Reference Flow to UVM World. This reference flow is a complete RISC-based SoC design plus a set of UVM Verification Components (UVCs), allowing users to learn about the UVM and execute their UVM testbench. The UVM Reference Flow is a subset of the Incisive Verification Kit, which provides powerful hands-on workshops, labs, and videos for comprehensive user understanding.
Just like with OVM, the real productivity gains with the UVM are when it is implemented in a metric-driven verification (MDV) flow, which leverages the power of constrained-random testing within a functional coverage environment with automation to ensure productivity. Feeding the MDV flow is Incisive Enterprise Simulator, which is performance-tuned for the UVM: it supports advanced UVM debug features, a UVM flow for low power, and the Incisive Verification IP portfolio, which comprises the industry’s broadest set of protocols supported by the unique Compliance Management System. Collectively, these flows and technologies deliver the ultimate solution for UVM users.
Features/Benefits
- Delivers an open, unified class library and methodology for interoperable VIP
- Eliminates the need for interoperability among multiple verification libraries
- Based on a base-class library proven in thousands of projects
- Integrates with the proven Metric-driven verification flow
- Provides built-in automation and testbench capabilities
- Supports module-to-system and project-to-project reuse
- Incorporates the collective verification knowledge of Accellera members
- Runs on any simulator supporting the IEEE 1800 standard
- Enables multi-language plug-and-play VIP
- Includes a methodology user guide and reference documentation
Resources