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Open Verification Methodology 

The Open Verification Methodology (OVM) is the first truly open, interoperable, and proven verification methodology. The OVM is an open-source SystemVerilog class library and methodology that defines a framework for reusable verification IP (VIP) and tests. It is 100% IEEE 1800 SystemVerilog and provides building blocks (objects) and a common set of verification-related utilities. The OVM release will be under the Apache 2.0 license, enabling anyone to use OVM libraries for any purpose, including creation of derivative work.

The OVM is jointly developed by Cadence and Mentor Graphics to facilitate true SystemVerilog interoperability with a standard library and a proven methodology. Completely open, it combines the best of the Cadence® Incisive® Plan-to-Closure Universal Reuse Methodology (URM) and the Mentor Advanced Verification Methodology (AVM), and is usable on two-thirds of the world's SystemVerilog systems. The OVM will also facilitate the development and usage of plug-and-play verification IP (VIP) written in SystemVerilog, SystemC®, and e languages.

For more information, please visit the OVM website.

The Open Verification Methodology (OVM) delivers the SystemVerilog interoperability promise



In December of 2009, Accellera selected the OVM to be the base of the emerging Universal Verification Methodology (UVM). The first version of the UVM, released in May of 2010, is based on OVM 2.1.1 with the “ovm_” names converted by a script to “uvm_” plus a few minor changes to the callbacks and end-of-test, but not to the core methodology or base classes. To learn more about the UVM, visit the Cadence UVM page.

Benefits:
  • First truly open, interoperable, and proven verification reuse methodology
  • Most advanced methodology, enabling multi-language plug-and-play VIP
  • Integrated with the proven Incisive Plan-to-Closure Methodology
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