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ECSM Library Format 

The Effective Current Source Model (ECSM) is designed to solve a key industry problem—how to accurately model delay where voltage fluctuations, process variation, and noise are acutely problematic. ECSM is the industry's first and only open standard current source model and enjoys broad industry support. It offers production-proven delay modeling for advanced low-power design and improved accuracy for timing sign-off. Having an open standard for modeling advanced nanometer effects enables collaboration between industry leaders to ease the transition to smaller process nodes.

The ECSM standard is the most complete open library format available and holistically models the effects of timing, noise, power, and variation. IP providers will benefit from greater simplicity and efficiency in the library creation process as well as a simplified distribution model. Users will also benefit from the simplified flow setup and library management that supports all of their sign-off modeling needs.

Delay Modeling
Modeling the voltage impact on delay can be particularly problematic for low-power applications. The ECSM timing model is an advanced cell driver model that represents the effect of non-linear switching waveforms on cell-based interconnect delay calculation and signal integrity. It has consistently demonstrated superior delay calculation accuracy by modeling a cell's output drive as a current source rather than a voltage source. Current sources are more effective at tracking non-linear transistor switching behavior and they permit highly accurate modeling of the complex interconnect common in today's largest low-power nanometer designs.

Precision delay calculation is achieved with ECSM by modeling the cell's output drive as a current source rather than a voltage source, enabling accurate modeling of non-linear transistor behavior. When this current driver model is coupled with ECSM's advanced receiver model that includes a multi-piece capacitance model the result is accuracy to within 2% of SPICE for:
  • Parallel drive networks
  • Varying supply voltages
  • Long interconnect
  • Miller effect
This is what makes ECSM is the production-proven delay model of choice for today's complex low-power and nanometer designs.

Noise Modeling
The risk of signal integrity related failures in silicon increases greatly at the 90nm process node and below. Using advanced Voltage-in/voltage-out relationships, the Noise Extensions enable Signal Integrity (SI) analysis tools to model the cumulative effects of noise introduced by coupling capacitances in complex scenarios where multi-Vt & multi-voltage devices commingle. The SI extensions are based on the cdB format, which is production proven in over 1000 tapeouts. When used in conjunction with Power and Timing extensions, the Noise Extensions to ECSM will accurately measure the cumulative impact of IR Drop and Noise on delay to provide a more holistic view of timing as well as power sign-off.

Power Modeling
ECSM Power modeling enables dynamic gate power-grid analysis, which provides actual current drawn from the power-grid at any given time for individual cells. The extension allows storage of current waveform at power-grid pins for different combinations of slew and load. Version 2.1 of ECSM specification was produced by the ECSM working group of the OMC (Open Modeling Coalition). This working group includes representatives from Cadence, Freescale, Intel, LSI Logic, Magma Design Automation, Silicon Navigator, Sun Microsystems and Virage Logic. The v2.0 specification is available for download from Si2.

Statisitcal Variation Modeling
Statistical analysis is necessary to enable designers to more efficiently manage the increasing process variations in manufacturing and sensitivity to process and environmental parameters that affect circuit performance at 65 nanometers and below. Standardization of the information required to support this analysis is key to rapid industry adoption. Cadence is collaborating with Magma Design Automation, Extreme DA, Altos Design Automation, ARM and Virage Logic to accelerate the creation of an open, standard statistical analysis library format under the Open Modeling Coalition of Si2. This open statistical library format will be based on current source models. In addition to enabling interoperability between design tools and methodologies for 65nm design and below, the intent is to create a comprehensive solution that will eliminate the need for designers to support multiple library formats—a time-consuming and costly undertaking that introduces errors into the design process and delays the delivery of complex integrated circuits (ICs).

Join the Si2 Open Modeling Coalition.