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Cadence and TSMC Library Distribution 

As leaders in their respective markets, TSMC and Cadence have been teaming up to provide a total nanometer design solution to our mutual customers. This solution integrates TSMC libraries with the Cadence Encounter® digital IC design platform, a qualified platform in TSMC Reference Flow 9.0, and bundle various key technology files that are pre-validated for optimum performance and quality. This is a methodology and service combination, design for manufacturability starting from gate level, all the way to final routed GDS. A nanometer design solution accelerates first time silicon success.

Cadence is a full-line distributor of the TSMC 40/45, 65, 90, 130, 150-nanometer and Nexsys 90-nanometer standard cell libraries and standard I/O libraries. These libraries available for download directly from Cadence website are developed by the excellent TSMC R&D team and are tuned to TSMC processes for optimal yield and manufacturability. In addition, we have added the next generation Universal I/O Library from TSMC sypporting CUP and RDL Flip Chip Technologies.

Press Releases and Success Stories
Available TSMC Libraries and Request form
  • Library Usage Agreement

  • 1.To download the Front-End View package, the customer must acknowledge TSMC Front-end Library Usage Agreement and agree the Term of Use specified in this document.
    2.To download the Back-End View package, the customer must sign and return the Back-end view Library Usage Agreement to Cadence before the request is approved.
  • Cost
  • TSMC standard cell and IO libraries are available at $0 cost to Cadence customers. Please contact your account manager for the maintenance cost on back-end views.