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Cadence and UMC Partnership 

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UMC is a world-leading foundry specializing in the contract manufacturing of customer-designed ICs for high-performance semiconductor applications. UMC delivers cutting-edge foundry technologies that enable the development of sophisticated SoC designs, including 0.13µ copper/low k, embedded DRAM, and mixed-signal/RFCMOS.

The Cadence & UMC partnership provides customers with a path to successfully implement designs using Cadence products with UMC's processes. Mutual customers can download interconnect extraction technology files for Cadence® Fire & Ice® QXC, Assura™ RCX, along with physical verification DRC, LVS rule decks for Assura, Dracula®,Diva, at MyUMC.

Click here for information on the UMC Silicon Shuttle Program.

Analog/mixed-signal reference flows
UMC and Cadence have jointly developed a silicon-proven Analog Reference Flow using the 0.18µ mixed-mode (MM) process design kit (PDK) from UMC. Based on the Cadence Virtuoso® custom design platform, the reference flow addresses the complexity of today's ICs and gives customers a starting point for their analog/mixed-signal designs. Since the flow is already UMC/Cadence-validated and optimized to UMC's 0.18µ MM process, it increases designer productivity, reduces development costs and re-spins, and ultimately accelerates time to market.

The UMC-Cadence Analog Reference Flow kit and 0.18µ MM PDK are currently available at no charge to Cadence/UMC customers. Contact your UMC sales representative or make an online request through MyUMC.For additional information on the Analog Reference Flow, download the datasheet.

Click here to check on UMC PDK availability.

Digital reference flows
Targeting SoC designs at 130nm and below, the UMC-Cadence Digital Reference Flow provides customers with a design methodology that enables customers to design products from concept into volume production. This RTL-to-GDSII flow takes a hierarchical design approach to addressing issues such as timing closure, signal and power integrity, and design for manufacturability.

Based on the Cadence Encounter™ digital IC design platform, the reference flow is silicon-validated using UMC's 130nm logic (CMOS) high-speed process along with IP/memories from Faraday Technology Corporation. The flow detects and eliminates any library or software issues early on, so customers can use the libraries and tools in their own design processes and are ensured of a low-risk, predictable path to silicon.

For additional information on the UMC-Cadence Digital Reference Flow, download the datasheet.

UMC Rule Deck