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Cadence and Tower Semiconductor Partnership 

Tower Semiconductor
Tower Semiconductor Ltd. is a pure-play independent specialty foundry established in 1993. The company manufactures integrated circuits with geometries ranging from 1.0 to 0.13-micron. Tower also provides complementary technical services and design support. In addition to digital CMOS process technology, Tower offers advanced embedded non-volatile memory solutions, and mixed-signal, RF, and CMOS image-sensor technologies.

To deliver world-class customer service, the company maintains two manufacturing facilities. Fab 1 has process technologies from 1.0 to 0.35 micron and can produce up to 16,000 150mm wafers per month. Fab 2 features 0.18-micron and below standard and specialized process technologies, and has a current capacity of up to 15,000 200mm wafers per month. The company has headquarters and fabs in Midgal Haemek, Israel, and sales and marketing offices in USA. Tower also works with a network of rep organizations in USA, Europe and Asia.

Analog and Mixed Signal Design Solutio
Tower continually partners with third parties that deliver high-quality design capabilities, IP, libraries and exceptional engineering services. This approach provides customers with a full set of tools and solutions that help them accelerate the design-to-silicon process and enhance first-time silicon success. By collaborating to provide out-of-the-box flows, and creating and qualifying superior PDKs, Tower and Cadence offer customers a faster path from design to volume production, at lower risk.

Reference flow for SoC designs using CMOS mixed signal process
An industry first in its breadth and depth, the TS18 Reference Flow is a complete, documented design—available to all Tower and Cadence mutual customers—taken through every step of the flow from specification to GDSII. The flow employs Cadence's digital and analog technologies spanning three Cadence platforms (Incisive, Virtuoso and Encounter) through Tower's PDKs and libraries.

By decreasing iterations in the design phase and improving accuracy through model optimization, the combined technologies enable a low-risk, predictable path from design to volume production.

Process technologies supported
Cadence Design Kit elements utilizing Tower's processes are available for:
  • 0.13-micron CMOS
  • 0.18-micron CMOS, Mixed Signal, embedded NVM and Image Sensor
  • 0.35-micron CMOS, Mixed Signal and Image Sensor
  • 0.50-micron CMOS, Mixed Signal, embedded NVM and Image Sensor
  • 0.60-micron CMOS
  • 0.80-micron CMOS
  • 1.00-micron CMOS
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Tower Semiconductor Rule Deck

Tower design kit and tech file availability SPICE LVS DRC Extraction
Feature Type Voltages Spectre Hspice Assura Dracula Assura Dracula Fire&Ice Assura
0.13 Logic 1.2/2.5/3.3 x x x - x - x x
0.13 MS 1.2/3.3/5.0 x x x - x - x x
0.18 Logic 1.8/3.3/5.0 x x x - x - x x
0.18 MS 1.8/3.3/5.0 x x x - x - x x
0.18 CIS 1.8/3.3/5.0 x x x - x - x x
0.18 NVM 1.8/3.3/5.0 x x x - x - x x
0.35 Logic 3.3/5.0 - x - x - x - -
0.35 MS 3.3/5.0 - x - x - x - -
0.35 CIS 3.3/5.0 - x - x - x - -
0.5 Logic 3.3/5.0 - x - x - x - -
0.5 MS 3.3/5.0 - x - x - x - -
0.5 CIS 3.3/5.0 - x - x - x - -
0.5 NVM 3.3/5.0 - x - x - x - -
0.6 Logic 5.0 - x - x - x - -