Home > Alliances > Foundry Program > Chartered

Email
Social Web

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Send yourself a copy

Cadence RSS Feeds

Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Send Yourself A Copy

Cadence and Chartered Partnership

Chartered Manufacturing, one of the world's top three silicon foundries, is forging a customized approach to outsourced semiconductor manufacturing by building lasting and collaborative design chain partnerships. As one of the early pioneers of the foundry model, Chartered has been delivering reliable and leading-edge manufacturing services to a broad spectrum of industries since 1987. Chartered operates five fabrication facilities including a state-of-the-art 300mm fab—all located in Singapore.

Under the Common Platform, Cadence with alliance partners Chartered, IBM and Samsung have qualified 65nm design solutions for earlier silicon validation and lower risk production of leading-edge integrated circuits (IC) and system-on-chip (SoC) devices.

Chartered customers can download technology files for QRC, Assura RCX; rule decks for Assura, Dracula and Diva DRC/LVS; and Spectre models for various processes through the Chartered Online Access System (COLAS). QRC technology files and Assura DRC/LVS/RCX rule decks for Chartered 65 nm process are available upon request from Chartered.

Digital IC design

Cadence and Common Platform partners have developed a 65nm low-power RTL-to-GDSII CPF-enabled Reference Flow. This Reference Flow is based on the Cadence Encounter Platform and is targeted to the Common Platform IBM-Chartered-Samsung 65nm low-power CMOS process. The flow addresses critical low-power design challenges, from chip prototyping through power, timing and area optimization and is targeted for wireless, wireline and consumer applications. The 65nm CPF-enabled reference flow kit can be accessed common_platform_65LP@cadence.com. This reference flow kit contains a reference design, documentation and scripts to run the reference flow. Additional information on the reference flow can be found in the common platform datasheet.

Mixed-Signal/RF Design

Chartered and Cadence have jointly developed Process Design Kits (PDKs) for several Chartered processes. PDKs provide the crucial link between foundry process data and the tools used in a custom analog and mixed-signal design methodology. The following PDKs are available from Chartered Semiconductor.

CHRT35SG - Single Gate Mixed Signal
CHRT35DG - Dual Gate Mixed Signal & RF
CHRT25MS - Mixed Signal & RF
CHRT18MS - Mixed Signal & RF
CHRT18IB - Logic Process
CHRT13LG - Logic Process
CHRT13RF - Mixed Signal & RF
CHRT90LP/G - Logic Process
CHRT65LP/G - Logic Process