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Announcing IP Talks! 2008: Meet With Leading IP Suppliers at DAC
Renesas Adopts Cadence SoC Encounter for Large Scale Complex Chips and Flip-Chip Design
Socle Technology, Inc. Adopts Cadence Low-Power Solution to Address 65nm Power Efficiency Challenges
How floorplanning guides synthesis and physical design
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SCD Source
DRC signoff doesn't cut it for next-gen nodes
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EE Times
Toward a standard deep sub-micron analog design flow: Cadence enhances the Virtuoso Platform
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EDN
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Cadence Kits
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